Floating body cell

1. A method comprising:

forming a silicon on insulator (SOI) layer on a substrate;

forming a band-engineered layer surrounding and/or on the SOI layer, the band-engineered layer formed as a multi-layer stack with a decreasing concentration of germanium (Ge) from a bottom surface of the multi-layer stack to a top surface of the multi-layer stack;

forming a silicon layer on the band-engineered layer;

forming a dummy gate on the silicon layer;

forming a source region and a drain region with at least one of the source region and the drain region being on the band-engineered layer; and

forming a gate on the SOI layer, between the source and drain regions, the gate formed by:

removing the dummy gate, the silicon layer and the band-engineered layer below the dummy gate, forming a cavity;

forming a gate oxide layer on sidewalls and a bottom surface of the cavity; and

filling the cavity with a gate material.

2. The method according to claim 1 , comprising:

forming the gate prior to the band-engineered layer;

forming a hard mask on the gate;

recessing the SOI layer forming recesses on each side of the gate;

forming the band-engineered layer lining the recesses;

forming the source region and the drain region on the band-engineered layer; and

removing the hard mask.

3. The method according to claim 2 , further comprising:

forming a gate oxide layer on the SOI layer prior to forming the gate; and

forming the source and drain regions coplanar with the gate oxide layer.

4. The method according to claim 1 , further comprising:

recessing the SOI layer;

forming a gate oxide layer on a sidewall and a bottom surface of the recess;

forming a gate on the gate oxide layer;

recessing the SOI layer on each side of the gate;

forming the band-engineered layer on the recessed SOI layer; and

forming the source region and the drain region on the band-engineered layer.

5. The method according to claim 1 , comprising:

forming a silicon layer on the band-engineered layer;

etching a portion of the silicon layer, the band-engineered layer, and the SOI layer;

forming a gate oxide layer on a sidewall and a bottom surface of the etched portion; and

forming a gate on the gate oxide layer, prior to forming the source and drain regions.

6. The method according to claim 1 , comprising:

forming a buried oxide (BOX) layer between the substrate and the SOI layer.

7. A device comprising:

a silicon on insulator (SOI) layer on a substrate;

a gate on the SOI layer;

a gate oxide layer on side and bottom surfaces of the gate;

a band-engineered layer on the SOI layer, on at least one side of the gate, the band-engineered layer formed as a multi-layer stack with a decreasing concentration of germanium (Ge) from a bottom surface of the multi-layer stack to a top surface of the multi-layer stack; and

a source region and a drain region at opposite sides of the gate, at least one of the source region and the drain region being on the band-engineered layer,

wherein the band-engineered layer is on both sides of the gate.

8. The device according to claim 7 , wherein:

the SOI layer is recessed on each side of the gate;

the band-engineered layer lining each recess; and

both the source region and the drain region are formed on the band-engineered layer.

9. The device according to claim 8 , wherein:

the source region and the drain region extend above a top surface of the SOI layer.

10. The device according to claim 7 , wherein:

a portion of the SOI layer is recessed;

a gate oxide layer lines a side surface and a portion of a bottom surface of the recess, forming an L-shape;

the gate is formed on the gate oxide layer; and

the band-engineered layer is on a non-recessed portion of the SOI layer.

11. The device according to claim 7 , comprising:

a first recess in the SOI layer having a first depth;

a gate oxide layer lining a side surface and a portion of a bottom surface of the first recess, forming an L-shape;

the gate being formed on the gate oxide layer;

a second recess in the SOI layer having a second depth, less than the first depth at one side of the gate;

a third recess in the SOI layer having a third depth at the other side of the gate,

wherein the band-engineered layer lines the second and third recesses and both the source region and the drain region are formed on the band-engineered layer.

12. The device according to claim 7 , further comprising a buried oxide (BOX) layer under the SOI layer.

13. A method comprising:

forming a buried oxide (BOX) layer on a silicon substrate;

forming a silicon on insulator (SOI) layer on the BOX layer;

forming a gate oxide,

forming a gate on the SOI layer;

forming a band-engineered layer on the SOI layer at least at one side of the gate, the band-engineered layer formed as a multi-layer stack with a decreasing concentration of germanium (Ge) from a bottom surface of the multi-layer stack to a top surface of the multi-layer stack;

forming a silicon layer on the band-engineered layer; and

forming source and drain regions at opposite sides of the gate, each in either the silicon layer or the SOI layer,

wherein the gate oxide layer is formed on a bottom surface and at least one side surface of the gate.