Method for fabricating semiconductor devices using stress engineering

1. A method for fabricating a semiconductor device comprising:

providing a substrate prepared with isolation regions;

forming a gate stack having first and second sidewalls over a substrate;

forming stressor diffusion extension regions within the substrate on opposed sides of the gate stack, wherein the stressor diffusion extension regions comprise a first concentration of stressor atoms incorporated into substitutional sites of diffusion extension regions;

forming source/drain (S/D) stressor diffusion regions on opposed sides of the gate stack within the substrate, wherein the S/D stressor diffusion regions comprise a depth which is deeper than the diffusion extension regions and comprise the first concentration of stressor atoms incorporated into substitutional sites of S/D diffusion regions;

forming a first stressor layer over the substrate after forming the stressor diffusion extension regions, the first stressor layer having a first stress value;

performing a first anneal to memorize at least a portion of the first stress value in the semiconductor device, wherein the first anneal is conducted at a low temperature; and

performing a second anneal with a laser based anneal to activate dopants in the S/D diffusion regions after the first anneal, wherein the first and second anneal prevent displacement of the stressor atoms having the first concentration from the substitutional sites and which are distributed throughout a width of diffusion extension and diffusion regions which extends from a sidewall of the gate to the isolation region.

2. The method of claim 1 , wherein the first anneal to memorize at least a portion of the first stress value is conducted at a temperature of 700° C. or less.

3. The method of claim 1 , wherein the first anneal to memorize at least a portion of the first stress value comprises annealing in a furnace environment.

4. The method of claim 1 , further comprising removing the first stressor layer after the first anneal to memorize at least a portion of the first stress value.

5. The method of claim 1 , wherein the diffusion extension regions are source/drain extension regions and the semiconductor device is a MOS transistor.

6. The method of claim 1 , wherein the stressor atoms comprise carbon.

7. The method of claim 1 comprising:

forming first spacers along sidewalls of the gate stack, wherein the first spacers act as a mask during the formation of the stressor diffusion extension regions such that edges of the stressor diffusion extension regions are aligned with outer edges of the first spacers.

8. The method of claim 1 wherein the diffusion extension regions are source/drain extension regions and the semiconductor device is a MOS transistor.

9. The method of claim 1 wherein the atomic concentration of stressor atoms incorporated into the substitutional sites is at least 1% post first and second anneal.

10. The method of claim 1 wherein forming the stressor diffusion extension regions comprises performing a laser anneal to incorporate the stressor atoms into the substitutional sites and to convert the stressor diffusion extension regions into crystalline stressor regions.

11. The method of claim 1 , wherein the second anneal comprises performing a laser spike anneal.

12. A method for fabricating a semiconductor device comprising:

providing a substrate prepared with isolation regions;

forming a gate stack having first and second sidewalls over a substrate;

forming stressor diffusion extension regions within the substrate on opposed sides of the gate stack, wherein the stressor diffusion extension regions are formed by implanting a first concentration of stressor atoms which are incorporated into substitutional sites of diffusion extension regions and distributed throughout a width of the diffusion extension regions; and

forming stressor diffusion regions by implanting the first concentration of stressor atoms which are incorporated into substitutional sites of diffusion regions and distributed throughout a width of the diffusion regions on opposed sides of the gate stack within the substrate, wherein the stressor diffusion regions comprise a depth which is deeper than a depth of the diffusion extension regions, and the stressor diffusion extension regions are located closer to an edge of the gate stack compared to the stressor diffusion regions, and wherein the first concentration of the stressor atoms are distributed throughout the width of diffusion extension and diffusion regions which extends from a sidewall of the gate to the isolation region.

13. The method of claim 12 , wherein forming the stressor diffusion extension regions comprises:

introducing first type dopants to form the diffusion extension regions; and

introducing the stressor atoms, wherein the stressor atoms are confined within the diffusion extension regions.

14. The method of claim 13 , wherein introducing the stressor atoms is performed after introducing the first type dopants.

15. The method of claim 13 , wherein:

introducing the stressor atoms comprises implanting the stressor atoms into the substrate; and comprises

annealing the substrate to incorporate the stressor atoms into the substitutional sites of the substrate.

16. The method of claim 15 , wherein the implant of the stressor atoms is tuned such that the stressor atoms are substantially confined within an upper portion of the diffusion extension regions.

17. The method of claim 15 , wherein the stressor atoms are incorporated into the substitutional sites of the substrate using laser annealing.

18. The method of claim 13 , comprising:

forming first spacers along sidewalls of the gate stack, wherein the first spacers act as a mask during introduction of the first type dopants and stressor atoms such that edges of the stressor diffusion extension regions are aligned with outer edges of the first spacers.

19. The method of claim 18 , wherein forming the stressor diffusion regions comprises:

forming second spacers along sidewalls of the first spacers;

introducing first type dopants to form the diffusion regions; and

introducing stressor atoms, wherein the stressor atoms are confined within the diffusion regions to form the stressor diffusion regions.

20. A semiconductor device comprising:

a substrate having isolation regions;

a gate stack having first and second sidewalls disposed over a substrate;

stressor diffusion extension regions within the substrate on opposed sides of the gate stack, wherein the stressor diffusion extension regions comprise a first concentration of stressor atoms incorporated in substitutional sites of diffusion extension regions and which are distributed throughout a width of the diffusion extension regions; and

stressor diffusion regions having the first concentration of stressor atoms which are incorporated into substitutional sites of diffusion regions and distributed throughout a width of the diffusion regions within the substrate on opposed sides of the gate stack, wherein the stressor diffusion regions comprise a depth which is deeper than a depth of the diffusion extension regions, and wherein the stressor diffusion extension regions are located closer to an edge of the gate stack compared to the stressor diffusion regions, and wherein the first concentration of the stressor atoms are distributed throughout a width of diffusion extension and diffusion regions which extends from a sidewall of the gate to the isolation region.

21. A method for fabricating a semiconductor device comprising:

providing a substrate prepared with isolation regions;

forming a gate stack having first and second sidewalls over a substrate;

forming stressor diffusion extension regions within the substrate on opposed sides of the gate stack, wherein the stressor diffusion extension regions comprise stressor atoms incorporated into substitutional sites of diffusion extension regions;

forming source/drain (S/D) diffusion regions, wherein the S/D diffusion regions comprise a depth which is deeper than the diffusion extension regions;

forming a first stressor layer over the substrate after forming the stressor diffusion extension regions, the first stressor layer having a first stress value;

performing a first anneal to memorize at least a portion of the first stress value in the semiconductor device, wherein the first anneal is conducted at a low temperature; and

performing a second anneal with a laser based anneal to activate dopants in the S/D diffusion regions after the first anneal, wherein the first and second anneal prevent displacement of the stressor atoms from the substitutional sites and which are distributed throughout a width of diffusion extension regions which extends from a sidewall of the gate to the isolation region.