Multi-time programmable non-volatile memory

1. A method comprising:

forming a select gate and a floating gate above a substrate, each over a first shallow trench isolation (STI) region, a doped region formed between a source and a drain, and a second STI region;

forming a metal layer over the floating gate; and

forming a pair of self-aligned contacts on the first and second STI regions on opposite sides of the doped region, respectively, and electrically connected to the metal layer.

2. The method according to claim 1 , further comprising:

forming a pair of spacers on opposite sides of the floating gate;

forming a hardmask above the floating gate and between the pair of spacers; and

forming the pair of self-aligned contacts partially covering the hardmask and one spacer of the pair spacers.

3. The method according to claim 2 , comprising:

forming the pair of spacers having rounded corners at top surfaces opposite the hardmask.

4. The method according to claim 2 , comprising:

forming the pair of spacers and the hardmask having co-planar top surfaces.

5. The method according to claim 1 , further comprising:

forming a second pair of self-aligned contacts on the first and second STI regions, on opposite sides of the doped region, respectively, along a second side of the floating gate across the floating gate from the first pair of self-aligned contacts and electrically connected to the first metal layer.

6. The method according to claim 5 , further comprising:

forming a pair of blocking layers on opposite sides of the floating gate;

forming a hardmask above the floating gate and between the pair of blocking layers; and

forming the first and second self-aligned contacts over the pair of blocking layers and partially covering the hardmask layer.

7. The method according to claim 6 , comprising:

forming the pair of blocking layers of oxide, oxide-nitride-oxide (ONO), or a combination thereof.

8. The method according to claim 1 , further comprising:

forming a second metal layer over the doped region, the source, and the drain and above the first metal layer; and

forming a bit line contact connecting the second metal layer and the drain.

9. A device comprising:

a doped region formed between a source and a drain within a substrate;

first and second shallow trench isolation (STI) regions on opposite sides of the doped region;

a select gate and a floating gate each over the first STI region, the doped region, and the second STI region;

a metal layer over the floating gate; and

a pair of self-aligned contacts formed along one side of the floating gate on the first and second STI regions on opposite sides of the doped region, respectively, and electrically connected to the metal layer.

10. The device according to claim 9 , further comprising:

a pair of spacers on opposite sides of the floating gate; and

a hardmask above the floating gate and between the pair of spacers,

wherein the pair of self-aligned contacts partially cover the hardmask and one spacer of the pair spacers.

11. The device according to claim 10 , comprising:

the pair of spacers having rounded corners at top surfaces opposite the hardmask layer.

12. The device according to claim 10 , comprising:

top surfaces of the pair of spacers and the hardmask being co-planar.

13. The device according to claim 9 , further comprising:

a second pair of self-aligned contacts formed on the first and second STI regions, on opposite sides of the doped region, respectively, along a second side of the floating gate across the floating gate from the first pair of self-aligned contacts and electrically connected to the first metal layer.

14. The device according to claim 13 , further comprising:

a pair of blocking layers on opposite sides of the floating gate; and

a hardmask above the floating gate and between the pair of blocking layers,

wherein the first and second self-aligned contacts are formed over the pair of blocking layers and partially cover the hardmask layer.

15. The device according to claim 9 , comprising:

the doped region including a P-type channel.

16. The device according to claim 9 , comprising:

the doped region including an N-type channel.

17. The device according to claim 9 , further comprising:

a second metal layer over the doped region, the source, and the drain and above the first metal layer; and

a bit line contact connecting the second metal layer and the drain.

18. A method comprising:

forming a select gate and a floating gate above a substrate, each over a first shallow trench isolation (STI) region, a doped region formed between a source and a drain, and a second STI region;

forming a first metal layer over the floating gate;

forming two pairs of self-aligned contacts on the first and second STI regions, respectively, electrically connected to the first metal layer with self-aligned contacts of each pair being on opposite sides of the floating gate and the two pairs of self-aligned contacts being on opposite sides of the doped region;

forming a second metal layer over the doped region, the source, and the drain and above the first metal layer; and

forming a bit line contact connecting the second metal layer and the drain.

19. The method according to claim 18 , further comprising:

forming a pair of spacers on opposite sides of the floating gate;

forming a hardmask above the floating gate and between the pair of spacers; and

forming each self-aligned contact of the two pairs of self-aligned contacts partially covering the hardmask and one spacer of the pair of spacers.

20. The method according to claim 18 , further comprising:

forming a pair of blocking layers on opposite sides of the floating gate;

forming a hardmask above the floating gate and between the pair of blocking layers; and

forming each self-aligned contact of the two pairs of self-aligned contacts partially covering the hardmask and one blocking layer of the pair of blocking layers.