Silicon-on-insulator integrated circuit devices with body contact structures
View Patent ↗Silicon-on-insulator integrated circuits including body contact structures and methods for fabricating the same are disclosed. A method for fabricating a silicon-on-insulator integrated circuit includes filling a plurality of first and second shallow isolation trenches with an insulating material to form plurality of first and second shallow trench isolation (STI) structures, and forming a gate structure over the semiconductor layer that includes a first portion disposed over and parallel to at least two of the plurality of second STI structures and a second portion disposed in between the at least two of the plurality of second STI structures. The method further includes forming contact plugs to a body contact region of the semiconductor layer. The body contact region comprises a portion of the semiconductor layer between at least one of the plurality of first STI structures and at least one of the plurality of second STI structures.
1. A silicon-on-insulator integrated circuit comprising:
a semiconductor substrate layer;
an oxide insulating material layer disposed over the substrate layer;
a semiconductor layer formed over the insulating material layer;
within the semiconductor layer, a plurality of parallel, spaced apart first shallow trench isolation (STI) structures that extend completely though the semiconductor layer to contact with the oxide insulating material layer;
within the semiconductor layer, a plurality of parallel, spaced apart second STI structures that extend only part-way into the semiconductor layer, wherein at least two of the plurality of second STI structures are provided such that no first STO structure is provided therebetween;
a plurality of body contact regions in the semiconductor substrate between at least one of the first and at least one of the second STI structures;
source/drain regions in the semiconductor substrate between the at least two of the plurality of second STI structures;
a gate structure having a first portion over the plurality of second STI structures and a second portion over the source/drain regions; and
contact plugs to the body contact regions, to the source/drain regions, and to the gate structure.
2. The integrated circuit of claim 1 , wherein the oxide insulating material comprises a high density plasma (HDP) oxide.
3. The integrated circuit of claim 1 , wherein the gate structure comprises a gate electrode disposed over a gate insulating layer.
4. The integrated circuit of claim 1 , wherein the contact plugs comprise a conductive material.
5. The integrated circuit of claim 1 , further comprising lightly-doped well regions in the semiconductor substrate between the at least two of the plurality of second STI structures.
6. The integrated circuit of claim 1 , further comprising an inter-level dielectric layer over the gate structure and the semiconductor layer, and in between the contact plugs.