IP Library Granted Patent US 9,276,041
Granted Patent B2
US 9,276,041 · App. 13/423,793 · Granted Mar 1, 2016

Three dimensional RRAM device, and methods of making same

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Quick Facts
Patent No.
US 9,276,041
App. No.
13/423,793
Granted
Mar 1, 2016
Kind
B2
Abstract

Disclosed herein are various embodiments of novel three dimensional RRAM devices, and various methods of making such devices. In one example, a device disclosed herein includes a first electrode for a first bit line comprising a variable resistance material, a second electrode for a second bit line comprising a variable resistance material and a third electrode positioned between the variable resistance material of the first bit line and the variable resistance material of the second bit line.

Claims (41)

1. An RRAM device, comprising:

a first electrode for a first bit line;

a second electrode for a second bit line;

a common electrode positioned between said first and second electrodes, said common electrode having first and second ends;

a diode coupled to said first end of said common electrode;

a first variable resistance material layer positioned between and contacting said first electrode and said common electrode; and

a second variable resistance material layer positioned between and contacting said second electrode and said common electrode.

2. The device of claim 1 , wherein said diode comprises a bipolar junction transistor.

3. The device of claim 2 , wherein said bipolar junction transistor is comprised of first, second and third doped layers of material, wherein said second doped layer of material is positioned between said first and third doped layers of material, and wherein said first and third doped layers of material are doped with a first type of dopant material and said second doped layer of material is doped with a second type dopant that is a type dopant that is opposite said first type of dopant, and wherein said device further comprises a conductive word line that is conductively coupled to said second doped layer of material.

4. The device of claim 1 , further comprising a conductive word line, wherein said diode is positioned between said conductive word line and said common electrode and wherein said diode is conductively coupled to both said conductive word line and said common electrode.

5. The device of claim 1 , wherein said diode comprises a first doped layer of material that is doped with a first type of dopant.

6. The device of claim 5 , further comprising a second doped layer of material that is positioned between said conductive word line and said common electrode, wherein said second doped layer is doped with a second type dopant that is a type dopant that is opposite said first type of dopant.

7. The device of claim 1 , wherein said diode is positioned in a first perpendicular orientation with respect to said common electrode.

8. The device of claim 7 , wherein said diode is positioned in a second perpendicular orientation with respect to said first and second electrodes.

9. The device of claim 1 , further comprising a structure having an upper surface, wherein said first variable resistance material is formed above said structure and has an upper surface that is substantially planar with an upper surface of said first electrode, is positioned at a level that is below a level of said upper surface of said common electrode, and is parallel with the upper surface of said structure, said second variable resistance material layer is formed above said structure and has an upper surface that is substantially planar with an upper surface of said second electrode, is positioned at a level that is below the level of said upper surface of said common electrode, and is parallel with the upper surface of said structure, and said common electrode is positioned perpendicular to the upper surface of said structure.

10. An RRAM device, comprising:

a first electrode for a first bit line comprising a variable resistance material;

a second electrode for a second bit line comprising a variable resistance material;

a third electrode having first and second ends and being positioned between and contacting said variable resistance material of said first bit line and said variable resistance material of said second bit line; and

a diode coupled to said first end of said third electrode.

11. The device of claim 10 , wherein said third electrode is a common electrode.

12. The device of claim 10 , wherein said diode comprises a bipolar junction transistor.

13. The device of claim 10 , further comprising a conductive word line, wherein said diode is positioned between said conductive word line and said third electrode and wherein said diode is conductively coupled to both said conductive word line and said third electrode.

14. The device of claim 13 , wherein said conductive word line is one of a first doped layer of material that is doped with a first type of dopant or a metal line.

15. The device of claim 10 , wherein said diode is positioned in a first perpendicular orientation with respect to said third electrode.

16. The device of claim 15 , wherein said diode is positioned in a second perpendicular orientation with respect to said first and second electrodes.

17. The device of claim 10 , further comprising a structure having an upper surface, wherein said first electrode and said first bit line are formed above said structure and have upper surfaces that are substantially planar with one another, are positioned at a first level, and are parallel with the upper surface of said structure, said second electrode and said second bit line are formed above said structure and have upper surfaces that are substantially planar with one another, are positioned at a second level that is substantially level with said first level, and are parallel with the upper surface of said structure, and said third electrode is positioned perpendicular to the upper surface of said structure and has an upper surface at said second end that is positioned at a third level that is above said first and second levels.

18. An RRAM device, comprising:

a plurality of stacked bit levels, wherein each bit level comprises:

a first electrode for a first bit line comprising a first variable resistance material;

a second electrode for a second bit line comprising a second variable resistance material;

a third electrode having first and second ends and that extends through said plurality of stacked bit levels, wherein, for each of said bit levels, said third electrode is positioned between and contacting said first variable resistance material of said first bit line and said second variable resistance material of said second bit line; and

a diode coupled to said first end of said third electrode.

19. The device of claim 18 , wherein said third electrode is a common electrode.

20. The device of claim 18 , further comprising and a conductive word line, wherein said diode is positioned between said conductive word line and said third electrode and wherein said diode is conductively coupled to both said conductive word line and said third electrode.

21. The device of claim 18 , further comprising a bipolar junction transistor that is conductively coupled to said third electrode.

22. The device of claim 18 , further comprising a conductive word line that is conductively coupled to an access/selector device.

23. The device of claim 22 , wherein said conductive word line is one of a first doped layer of material that is doped with a first type of dopant or a metal line.

24. The device of claim 18 , wherein said diode is positioned in a first perpendicular orientation with respect to said third electrode.

25. The device of claim 24 , wherein said diode is positioned in a second perpendicular orientation with respect to said first and second electrodes.

26. The device of claim 18 , further comprising a structure, wherein said first variable resistance material is formed above said structure and has an upper surface that is substantially planar with an upper surface of said first electrode and parallel to the upper surface of said structure, wherein said second electrode is formed above said structure, has an upper surface that is substantially planar with an upper surface of said second variable resistance material, and is parallel with said upper surface of said structure, and said third electrode is positioned perpendicular to said upper surface of said structure.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Nov 19, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Reel/Frame 054481/0673 →
SECURITY AGREEMENT Recorded Nov 27, 2018
From: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 047660/0203 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2012
From: TOH, ENG HUAT; QUEK, ELGIN; TAN, SHYUE SENG
To: GLOBALFOUNDRIES SINGAPORE PTE LTD
Reel/Frame 027886/0726 →