Method for fabricating semiconductor devices with reduced junction diffusion
View Patent ↗A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling.
1. A method for forming a device comprising:
providing a substrate;
implanting first type dopants in the substrate to form a first doped region, wherein the first doped region as formed includes
a crystalline vacancy rich region, and
a buried amorphous region, wherein the vacancy rich region extends from the surface of the substrate to a top of the buried amorphous region;
implanting second type dopants having a second polarity into the substrate to form a second doped region, wherein the second doped region is contained within the first doped region and overlaps both the vacancy rich and buried amorphous regions, and a peak second dopant concentration is located at a depth Rpd from the surface of the substrate, wherein the vacancy rich region has a depth that is greater than or equal to Rpd;
recrystallizing the buried amorphous regions; and
activating the second type dopants in the second doped region, wherein the crystalline upper vacancy rich region has a sufficient amount of excess vacancies to improve electrical activation in the second doped region above the solid solubility limit.
2. The method in claim 1 wherein the first doped region comprises a halo region.
3. The method in claim 1 wherein the second doped region comprises a diffusion region.
4. The method in claim 1 wherein implanting the first type dopants comprising injecting dopants into the substrate at angle to an axis transverse to the surface of the substrate.
5. The method in claim 1 wherein the vacancy rich region has a depth of about Rpd to 3 Rpd.
6. The method in claim 1 wherein the vacancy rich region has a depth of about Rpd to 2 S σ , S σ being the depth where the dopant concentration drops to 1/e 0.5 of the maximum dopant concentration.
7. The method in claim 1 wherein the vacancy rich region has a depth of about 1 to 10 nanometers.
8. A method for forming a device comprising:
providing a substrate;
implanting first type dopants in the substrate to form a first doped region, wherein the first doped region as formed includes
a crystalline vacancy rich region, and
a buried amorphous region, wherein the vacancy rich region extends from the surface of the substrate to a top of the buried amorphous region;
implanting second type dopants having a second polarity into the substrate to form a second doped region, wherein the second doped region overlaps both the vacancy rich and buried amorphous regions;
activating the second type dopants in the second doped region, wherein the crystalline upper vacancy rich region has a sufficient amount of excess vacancies to improve electrical activation in the second doped region above the solid solubility limit.
9. The method in claim 8 wherein implanting the first type dopants in the substrate comprises forming first doped regions adjacent to a gate stack on the substrate.
10. The method in claim 9 wherein the first doped regions are isolated from each other by a portion of the substrate under the gate stack.
11. The method in claim 10 wherein implanting the second type dopants into the substrate comprises forming second doped regions which are contained within the first doped regions.
12. The method in claim 11 wherein implanting the first type dopants comprises implanting dopants at a dose that is less than a dose used in forming the second doped regions.
13. The method in claim 8 wherein the second type dopants comprise a peak concentration located at a depth Rpd from the surface of the substrate, wherein the vacancy rich region has a depth that is greater than or equal to Rpd.
14. The method in claim 11 wherein the substrate comprises a buried insulating region, the first and second doped regions being located above the insulating region.
15. The method in claim 14 wherein the buried amorphous region abuts the buried insulating region.
16. The method in claim 14 wherein the buried insulating region is a buried nitride or buried oxide layer.
17. The method in claim 8 wherein:
the substrate comprises a crystalline on insulator substrate having a crystalline surface substrate separated by a crystalline bulk substrate by an insulator layer;
the first doped regions extend below the insulator layer into the bulk substrate, wherein
the crystalline upper vacancy rich region is disposed in the surface substrate, and
the lower buried amorphous region extends from the surface substrate into the bulk substrate; and
the second doped regions are disposed in the surface substrate.
18. The method in claim 8 wherein the first doped region comprises a halo region.
19. The method in claim 8 wherein the second doped region comprises a diffusion region.
20. A method for forming a device comprising:
providing a substrate having a buried insulating region;
implanting first type dopants in the substrate to form a first doped region, wherein the first doped region as formed includes
a crystalline vacancy rich region, and
a buried amorphous region, wherein the vacancy rich region extends from the surface of the substrate to a top of the buried amorphous region;
implanting second type dopants having a second polarity into the substrate to form a second doped region, wherein the second doped region overlaps both the vacancy rich and buried amorphous regions;
activating the second type dopants in the second doped region, wherein the crystalline upper vacancy rich region has a sufficient amount of excess vacancies to improve electrical activation in the second doped region above the solid solubility limit.