IP Library Granted Patent US 8,264,088
Granted Patent B2
US 8,264,088 · App. 13/179,573 · Granted Sep 11, 2012

Planarized passivation layer for semiconductor devices

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Quick Facts
Patent No.
US 8,264,088
App. No.
13/179,573
Granted
Sep 11, 2012
Kind
B2
Abstract

A semiconductor device includes a substrate having a dielectric layer and a device layer on the substrate. The device layer has an opening. First and second sublayers are disposed on the device layer and line the opening. The second sublayer serves as a stop layer for planarization to provide a substantially planarized top surface for the semiconductor device.

Claims (17)

1. A device comprising:

a substrate with a device layer having a trench opening;

a first sublayer over a top surface of the device layer;

a fill layer to fill the opening, wherein a top surface of a fill material of the fill layer is substantially planar with a top surface of the first sublayer; and

a second sublayer, wherein the second sublayer lines a bottom and sidewalls of the trench opening and the second sublayer in the trench is recessed below the top surface of the first sublayer and the top surface of the fill material.

2. The device of claim 1 further includes a surface passivation layer on the surface of the substrate, wherein the surface passivation layer covers the first sublayer, recessed second sublayer and the fill material.

3. The device of claim 1 wherein the first sublayer serves as a passivation layer to protect the device layer.

4. The device of claim 1 wherein the first second sublayer comprises nitride.

5. The device of claim 4 further includes a surface passivation layer on the surface of the substrate, wherein the surface passivation layer covers the first sublayer, recessed second sublayer and the fill material.

6. The device of claim 5 wherein the surface passivation layer includes a plurality of sublayers.

7. The device of claim 1 wherein the device layer comprises a reflective layer.

8. The device of claim 7 wherein the reflective layer comprises a conductive material.

9. The device of claim 1 wherein the first sublayer comprises oxide.

10. The device of claim 9 wherein the second sublayer comprises nitride.

11. The device of claim 9 further includes a surface passivation layer on the surface of the substrate, wherein the surface passivation layer covers the first sublayer, recessed second sublayer and the fill material.

12. The device of claim 11 wherein the surface passivation layer includes a plurality of sublayers.

13. The device of claim 11 wherein the surface passivation layer comprises silicon nitride or silicon oxynitride.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 19, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Reel/Frame 054481/0673 →
SECURITY AGREEMENT Recorded Nov 27, 2018
From: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 047660/0203 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 13, 2012
From: LIM, SIN LENG; KIM, IN KI; PARK, JONG SUNG; KIM, MIN HWAN; LU, WEI
To: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
Reel/Frame 028771/0070 →
CHANGE OF NAME Recorded Aug 13, 2012
From: CHARTERED SEMICONDUCTOR MANUFACTURING PTE. LTD.
To: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Reel/Frame 028771/0114 →
CHANGE OF NAME Recorded Aug 13, 2012
From: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
To: CHARTERED SEMICONDUCTOR MANUFACTURING PTE. LTD.
Reel/Frame 028771/0116 →