High gain device

1. A method of forming a device comprising:

providing a substrate having a core device region and a high gain (HG) device region for a HG transistor;

forming a core gate on the substrate in the core device region and a HG gate on the substrate in the HG device region, wherein the HG gate includes sidewall spacers on its sidewalls, wherein

the core gate and HG gate include gate dielectric and gate electrode layers, and

the gate dielectric layers of the core gate and HG gate comprise the same thickness;

performing a lightly doped drain (LDD) implant, the LDD implant implants first polarity type dopants to form first polarity type LDD regions adjacent to the core gate, the first polarity type comprises n-type; and

performing a source/drain (S/D) implant, the S/D implant implants first polarity type dopants to form heavily doped first polarity type core S/D regions adjacent to the core gate and heavily doped first polarity type HG S/D regions adjacent to the HG gate, the core device region includes core S/D regions with LDD regions while the HG device region includes HG S/D regions without LDD regions.

2. The method of claim 1 wherein the HG transistor comprises a channel which is disposed under the HG gate and the channel length of the HG gate is at least about 0.5 μm.

3. The method of claim 1 comprising forming sidewall spacers on gate sidewalls of the core gate in the core device region.

4. The method of claim 1 comprising:

providing a mask having an opening exposing the core device region while covering the HG device region on the substrate; and

performing an implant to form second polarity type halo regions in the core device region.

5. The method of claim 1 comprising forming halo regions in the core device region.

6. A method of forming a device comprising:

providing a substrate having at least a first device region for a first transistor and a second device region for a second transistor, wherein the first and second device regions comprise first polarity type devices, the first polarity type comprises n-type, wherein the first transistor comprises a core transistor and the second transistor comprises a high gain (HG) transistor;

forming a first gate on the first device region and a second gate on the second device region, the gates include sidewall spacers on their sidewalls, wherein forming the first gate and the second gate comprises

forming a gate dielectric layer on a top surface of the substrate and a gate electrode layer over the gate dielectric layer, and

patterning the gate dielectric and gate electrode layers to form the first and second gates, wherein the gate dielectrics of the first and second gate comprise the same thickness;

forming first polarity type lightly doped drain (LDD) regions; and

performing a source/drain (S/D) implant to form first polarity type heavily doped S/D regions adjacent to the first and second gates, wherein the first device region includes first S/D regions with LDD regions while the second device region includes second S/D regions without LDD regions.

7. The method of claim 6 wherein the HG transistor comprises a channel which is disposed under the second gate and the channel length of the second gate is at least about 0.5 μm.

8. The method of claim 6 comprising:

providing a mask having an opening exposing the first device region while covering the second device region on the substrate; and

performing an implant to form the first polarity type LDD regions in the first device region.

9. The method of claim 8 wherein inner edges of the first polarity type LDD regions adjacent to sides of the first gate are aligned with about sidewalls of the first gate.

10. The method of claim 8 wherein the implant to form the first polarity type LDD regions comprises an angled implant and inner edges of the LDD regions extend under sidewalls of the first gate.

11. The method of claim 8 comprising:

performing an implant to form second polarity type halo regions in the first device region.

12. The method of claim 11 wherein the implant to form the second polarity type halo regions is performed before the implant to form the first polarity type LDD regions.

13. A method of forming a device comprising:

providing a substrate having a core device region for a core transistor and a high gain (HG) device region for a HG transistor, wherein the core and HG device regions comprise first polarity type devices which is n-type;

forming a core gate on the substrate in the core device region and a HG gate on the substrate in the HG device region, wherein the core gate and the HG gate include sidewall spacers on their sidewalls, wherein

the core gate and HG gate include gate dielectric and gate electrode layers, and

the gate dielectric layers of the core gate and HG gate comprise the same thickness;

forming first polarity type lightly doped drain (LDD) regions only in the core device region, wherein inner edges of the LDD regions are aligned with about sidewalls of the core gate; and

performing a source/drain (S/D) implant to form first polarity type heavily doped S/D regions adjacent to the core and HG gates, the core device region includes core S/D regions with LDD regions while the HG device region includes HG S/D regions without LDD regions.

14. A method of forming a device comprising:

providing a substrate having a core device region for a core transistor and a high gain (HG) device region for a HG transistor;

forming a gate on the substrate in the core device region and a HG gate on the substrate in the HG device region, wherein

the gate and the HG gate include sidewall spacers on their sidewalls, and

the core transistor comprises a channel length which is less than about 0.18 μm and the HG transistor comprises a channel length which is at least about 0.5 μm; and

forming lightly doped drain (LDD) regions only in the core device region, wherein inner edges of the LDD regions are aligned with about sidewalls of the gate.

15. The method of claim 13 wherein forming the first polarity type LDD regions comprises:

providing a mask having an opening exposing the core device region while covering the HG device region on the substrate; and

performing an implant to form the first polarity type LDD regions only in the core device region.

16. The method of claim 15 wherein inner edges of the heavily doped regions are aligned with about outer edges of the sidewall spacers of the gates.