Structures and methods of improving reliability of non-volatile memory devices
View Patent ↗In one example, the memory device disclosed herein includes a gate insulation layer and a charge storage layer positioned above the gate insulation layer, wherein the charge storage layer has a first width. The device further includes a blocking insulation layer positioned above the charge storage layer and a gate electrode positioned above the blocking insulation layer, wherein the gate electrode has a second width that is greater than the first width. An illustrative method disclosed herein includes forming a gate stack for a memory device, wherein the gate stack includes a gate insulation layer, an initial charge storage layer, a blocking insulation layer and a gate electrode, and wherein the initial charge storage layer has a first width. The method further includes performing an etching process to selectively remove at least a portion of the initial charge storage layer so as to produce a charge storage layer having a second width that is less than the first width of the initial charge storage layer.
1. A memory device, comprising:
a gate insulation layer;
a charge storage layer positioned above the gate insulation layer, said charge storage layer having a first width;
a blocking insulation layer positioned above said charge storage layer;
a gate electrode positioned above said blocking insulation layer, said gate electrode having a second width that is greater than said first width; and
a sidewall spacer positioned adjacent to and laterally confining each of said gate insulation layer, said charge storage layer, said blocking insulation layer, and said gate electrode, wherein said sidewall spacer, said gate insulation layer, and said blocking insulation layer at least partially define a first gap that is positioned laterally adjacent to at least a first edge of said charge storage layer.
2. The device of claim 1 , wherein said first width is approximately 70-90% of said second width.
3. The device of claim 1 , wherein said charge storage layer is comprised of silicon nitride and said gate electrode is comprised polysilicon.
4. The device of claim 1 , wherein said charge storage layer is comprised of a conductive material.
5. The device of claim 1 , wherein said charge storage layer and said gate electrode are made of the same material.
6. The device of claim 1 , wherein said first edge of said charge storage layer is laterally and inwardly offset relative to a first sidewall of said gate electrode, and wherein said first sidewall is substantially aligned with respective first edges of said gate insulation layer and said blocking insulation layer.
7. The device of claim 6 , wherein said first gap is an air pocket.
8. The device of claim 6 , further comprising a layer of insulating material positioned between at least said sidewall spacer and said first sidewall of said gate electrode, said layer of insulating material substantially filling said first gap.
9. The device of claim 1 , wherein a second edge of said charge storage layer is laterally and inwardly offset relative to a second sidewall of said gate electrode, wherein said second sidewall is substantially aligned with respective second edges of said gate insulation layer and said blocking insulation layer, and wherein said sidewall spacer, said gate insulation layer, and said blocking insulation layer further at least partially define a second gap that is positioned laterally adjacent to at least said second edge of said charge storage layer.
10. The device of claim 9 , wherein said first and second gaps are air pockets.
11. The device of claim 9 , further comprising a layer of insulating material positioned between at least said sidewall spacer and said first and second sidewalls of said gate electrode, said layer of insulating material substantially filling said first and second gaps.
12. The device of claim 1 , wherein a second edge of said charge storage layer is substantially aligned with a second sidewall of said gate electrode.
13. A device, comprising:
a gate insulation layer having a first width;
a charge storage layer positioned above the gate insulation layer;
a blocking insulation layer positioned above said charge storage layer, said blocking insulation layer having a width that is the same as said first width;
a gate electrode positioned above said blocking insulation layer, said gate electrode having a second width that is greater than said first width; and
a sidewall spacer positioned adjacent to sidewalls of said gate electrode, said sidewall spacer laterally confining each of said gate insulation layer, said charge storage layer, said blocking insulation layer, and said gate electrode.
14. The device of claim 13 , further comprising a gap proximate opposite ends of each of said gate insulation material and said blocking insulation material, each of said gaps being substantially free of any solid material, wherein each of said opposite ends of said gate insulation material and said blocking insulation material are laterally and inwardly offset relative to a respective sidewall of said gate electrode.
15. The device of claim 14 , wherein each of said gaps is at least partially defined by said sidewall spacer and a respective laterally offset opposite end of a respective one of said gate insulation material and said blocking insulation layer.
16. A memory device, comprising:
a gate insulation layer positioned above an active layer of a semiconducting substrate, said gate insulation layer having first and second edges;
a blocking insulation layer positioned above said gate insulation layer, said blocking insulation layer having first and second edges;
a gate electrode positioned above said blocking insulation layer, said gate electrode having first and second sidewalls;
a charge storage layer positioned between said gate insulation layer and said blocking insulation layer, said charge storage layer having first and second edges, wherein a first edge of said charge storage layer is laterally and inwardly offset from said first edge of said gate insulation layer, said first edge of said blocking insulation layer, and said first sidewall;
a first spacer positioned adjacent to said first sidewall and said respective first edges of said gate insulation layer, said charge storage layer, and said blocking insulation layer, wherein said gate insulation layer, said blocking insulation layer, and said first spacer at least partially define a first gap that is positioned laterally adjacent to at least said first edge of said charge storage layer; and
a second spacer positioned adjacent to said second sidewall and said respective second edges of said gate insulation layer, said charge storage layer, and said blocking insulation layer, said first and second spacers laterally confining each of said gate insulation layer, said charge storage layer, said blocking insulation layer, and said gate electrode.
17. The device of claim 16 , wherein said respective first edges of said gate insulation layer and said blocking insulation layer are substantially aligned with said first sidewall.
18. The device of claim 17 , further comprising a layer of insulating material positioned between said first spacer and said substantially aligned first edges and first sidewall, said layer of insulating material substantially filling said first gap.
19. The device of claim 17 , wherein said first spacer is positioned on and in contact with said substantially aligned first edges and first sidewall, and wherein said first gap is substantially free of solid material.
20. The device of claim 16 , wherein said respective second edges of said gate insulation layer, said charge storage layer, and said blocking insulation layer are substantially aligned with said second sidewall, and wherein said second spacer is positioned on and in contact with said substantially aligned second edges and second sidewall.
21. The device of claim 16 , wherein said second edge of said charge storage layer is laterally and inwardly offset from said second edge of said gate insulation layer, said second edge of said blocking insulation layer, and said second sidewall, and wherein said gate insulation layer, said blocking insulation layer, and said second spacer at least partially define a second gap that is positioned laterally adjacent to at least said second edge of said charge storage layer.
22. The device of claim 21 , wherein said first and second gaps are substantially free of solid material.
23. The device of claim 21 , further comprising:
a first layer of insulating material positioned between said first spacer and each of said first sidewall and said respective first edges of said gate insulation layer and said blocking insulation layer, said first layer of insulating material substantially filling said first gap; and
a second layer of insulating material positioned between said second spacer and each of said second sidewall and said respective second edges of said gate insulation layer and said blocking insulation layer, said second layer of insulating material substantially filling said second gap.