IP Library Granted Patent US 8,450,046
Granted Patent B2
US 8,450,046 · App. 12/392,093 · Granted May 28, 2013

Methods for enhancing photolithography patterning

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,450,046
App. No.
12/392,093
Granted
May 28, 2013
Kind
B2
Abstract

A method for fabricating a semiconductor device that includes: providing a substrate prepared with a photoresist layer; providing a photomask comprising a first and a second pattern having a respective first and second pitch range; providing a composite aperture comprising a first and a second off-axis illumination aperture pattern, the first off-axis aperture pattern having a configuration that improves the process window of the first pitch range and the second off-axis aperture pattern having a configuration that improves the process window for a second pitch range; exposing the photoresist layer on the substrate with radiation from an exposure source through the composite aperture and the photomask; and developing the photoresist layer to pattern the photoresist layer.

Claims (27)

1. A method for fabricating a semiconductor device comprising:

providing a substrate prepared with a photoresist layer;

providing a photomask comprising a first and a second pattern having a respective first and second pitch range;

providing a composite aperture comprising first and second off-axis illumination (OAI) components, the first and second OAI components having respective first and second OAI aperture pattern, the first off-axis illumination aperture pattern having a configuration that reduces forbidden pitch effect of the first pitch range and the second off-axis illumination aperture pattern having a configuration that reduces forbidden pitch of the second pitch range;

exposing the photoresist layer on the substrate with radiation from a radiation source through the composite aperture and the photomask; and

developing the photoresist layer to pattern the photoresist layer.

2. The method as claimed in claim 1 , wherein the first and second off-axis illumination aperture patterns belong to the same off-axis illumination mode.

3. The method as claimed in claim 2 , wherein the first off-axis illumination aperture pattern comprises openings that are of a different thickness from openings associated with the second off-axis illumination aperture pattern.

4. The method as claimed in claim 3 , wherein thickness of the off-axis illumination aperture pattern openings is denoted by difference between partial coherence values of an inner and outer circumference of the openings.

5. The method as claimed in claim 2 , wherein the first and second off-axis illumination aperture patterns are oriented at an angle with respect to each other.

6. The method as claimed in claim 2 , wherein at least one of the first and second off-axis illumination aperture pattern belongs to an annular, dipole, quasar or quadrupole illumination mode.

7. The method as claimed in claim 1 , wherein the first off-axis illumination aperture pattern comprises openings that are of a different thickness from openings associated with the second off-axis illumination aperture pattern.

8. The method as claimed in claim 1 , wherein at least one of the first and second off-axis illumination aperture pattern belongs to an annular, dipole, quasar or quadrupole illumination mode.

9. The method as claimed in claim 1 , wherein the process window is defined by at least one of depth of focus, exposure latitude, and image contrast or weighted combinations thereof.

10. The method as claimed in claim 1 , wherein during photoresist exposure, radiation from the exposure source is sufficient to cause a total phase change in the entire thickness of the photoresist layer, wherein the first and second pattern is transferred onto the photoresist layer in a single exposure step.

11. The method as claimed in claim 1 , wherein the first and second patterns comprise line and space features.

12. The method as claimed in claim 1 , wherein the first and second patterns comprise openings.

13. The method as claimed in claim 1 , wherein the semiconductor device comprises an integrated circuit.

14. A method for fabricating a semiconductor device comprising:

providing a substrate prepared with a photoresist layer;

providing a photomask comprising first and second patterns having a respective first and second pitch range;

providing an aperture comprising first and second illumination components having respective first and second illumination aperture pattern, wherein the first and second illumination aperture patterns belong to the same illumination mode, the first illumination aperture pattern further having a configuration that reduces the forbidden pitch effect of the first pitch range and the second illumination aperture pattern having a configuration that reduces the forbidden pitch effect of the second pitch range;

exposing the photoresist layer on the substrate with radiation from a radiation source through the aperture and the photomask; and

developing the photoresist layer to pattern the photoresist layer.

15. The method as claimed in claim 14 , wherein the first illumination aperture pattern comprises openings that are of a different thickness from openings associated with the second illumination aperture pattern.

16. The method as claimed in claim 15 , wherein thickness of the illumination aperture pattern openings is denoted by difference between partial coherence values of an inner and outer circumference of the openings.

17. The method as claimed in claim 14 , wherein at least one of the first and second illumination aperture pattern belongs to an annular, dipole, quasar or quadrupole illumination mode.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 19, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Reel/Frame 054481/0673 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 19, 2020
From: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 054600/0031 →
RELEASE OF SECURITY INTEREST Recorded Nov 18, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054475/0718 →
SECURITY AGREEMENT Recorded Nov 27, 2018
From: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 047660/0203 →
CHANGE OF NAME Recorded Apr 22, 2013
From: CHARTERED SEMICONDUCTOR MANUFACTURING PTE. LTD.
To: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Reel/Frame 030257/0566 →
CHANGE OF NAME Recorded Apr 22, 2013
From: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
To: CHARTERED SEMICONDUCTOR MANUFACTURING PTE. LTD.
Reel/Frame 030257/0535 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 27, 2009
From: LING, MOH LUNG; TAY, CHO JUI; QUAN, CHENGGEN
To: NATIONAL UNIVERSITY OF SINGAPORE
Reel/Frame 022458/0720 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 27, 2009
From: CHUA, GEK SOON; LIN, QUNYING
To: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
Reel/Frame 022458/0726 →