Patent Assignment
Reel/Frame 054600/0031
Assignment of Assignor's Interest
Recorded: 2020-11-19
Pages: 53
Assignor
GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Executed: 2020-05-15
Assignee
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
NO. 8, LI-HSIN RD. 6, HSINCHU SCIENCE PARK, HSINCHU, 300-78, TAIWAN
Covered Properties
(40)
Mask and Method to Pattern Chromeless Phase Lithography Contact Hole
Poly Profile Engineering to Modulate Spacer Induced Stress for Device Enhancement
Statistical Optical Proximity Correction
Thin Film Etching Method and Semiconductor Device Fabrication Using Same
Method for Fabricating Device Structures Having a Variation in Electrical Conductivity
Methods for Normalizing Strain in a Semiconductor Device
Method for Reducing Silicide Defects in Integrated Circuits
Method of Forming a Nanostructure
System for Determining Potential Lot Consolidation During Manufacturing
Semiconductor Fabrication Process Including an Sige Rework Method
Methods for Enhancing Photolithography Patterning
Laser Annealing
Integrated Circuit Communication System with Differential Signal and Method of Manufacture Thereof
Mask System Employing Substantially Circular Optical Proximity Correction Target and Method of Manufacture Thereof
Integrated Circuit System with Sub-Geometry Removal and Method of Manufacture Thereof
Double Anneal with Improved Reliability for Dual Contact Etch Stop Liner Scheme
Control Gate
Methods for Reducing Loading Effects During Film Formation
Liquid Immersion Scanning Exposure System Using an Immersion Liquid Confined Within a Lens Hood
Memory Cell with Improved Retention
Selective Sti Stress Relaxation Through Ion Implantation
Novel Method to Tune Narrow Width Effect with Raised S/D Structure
Method for Reducing Silicide Defects in Integrated Circuits
Strained Channel Transistor and Method of Fabrication Thereof
Dielectric Stack
Semiconductor Structure Including High Voltage Device
Poly Profile Engineering to Modulate Spacer Induced Stress for Device Enhancement
Methods for Pfet Fabrication Using Apm Solutions
Esd Protection Without Latch-Up
Integrated Circuit System with Sub-Geometry Removal and Method of Manufacture Thereof
Tunneling Transistor
Etch Failure Prediction Based on Wafer Resist Top Loss
Dielectric Stack
Rram Cell with Bottom Electrode(S) Positioned in a Semiconductor Substrate
Methods for Fabricating Integrated Circuits Using Chemical Mechanical Polishing
Control Gate
Integrated Circuits with Laterally Diffused Metal Oxide Semiconductor Structures and Methods for Fabricating the Same
Methods for Fabricating Integrated Circuits with Low, Medium, and/or High Voltage Transistors on an Extremely Thin Silicon-on-Insulator Substrate
Patent:
9,653,365 →
Application:
15/093,888 →
Integrated Circuit Electrostatic Discharge Protection
Method and System for Detecting a Coolant Leak in a Dry Process Chamber Wafer Chuck
Related Assignments
(3)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Agreement
Nov 27, 2018
From: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 047660/0203 →
Release of Security Interest
Nov 18, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054475/0718 →
Release of Security Interest
Nov 19, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Reel/Frame 054481/0673 →