Integrated circuit electrostatic discharge protection
Integrated circuits with electrostatic discharge (ESD) protection and methods of providing ESD protection in an integrated circuit are provided. An ESD protection circuit the ESD protection circuit may incorporate a transistor, such as a MOSFET, and a voltage limiter coupled to a gate of the transistor. The voltage limiter may be configured such that with an ESD disturbance on the voltage supply rail, Vdd, a gate voltage of the transistor of the ESD protection circuit is held below the supply voltage (Vdd) inducing base current, Isub, within the transistor to effectively shunt a current arising from the ESD event from the voltage supply rail Vdd to the voltage supply rail Vss.
1. An integrated circuit electrostatic discharge protection circuit comprising:
a transistor having a drain operatively coupled to a first rail of the integrated circuit and a source operatively coupled to a second rail of the integrated circuit;
a trigger circuit operatively coupled to drive a gate of the transistor in response to an ESD event occurring on one of the first and second rails, wherein
the trigger circuit includes a voltage limiter operatively coupled from the gate to the source of the transistor the voltage limiter selectively limiting the gate voltage to a voltage less than a full turn on voltage of the transistor, wherein the gate voltage is selected to maximize a parasitic current flow within a parasitic bipolar transistor component of the transistor responsive to the ESD event.
2. The integrated circuit of claim 1 , wherein the first rail has a voltage, Vdd, wherein Vdd is equal to 2.5 volts (V), and the voltage limiter is configured to limit the voltage to the gate to 1V or less.
3. The integrated circuit of claim 1 , wherein the voltage limiter is configured to limit the voltage to the gate such that the transistor is not fully turned on.
4. The integrated circuit of claim 1 , wherein the voltage limiter comprises a diode.
5. The integrated circuit of claim 1 , wherein the voltage limiter comprises a plurality of diodes arranged in series.
6. A method providing electrostatic discharge protection in an integrated circuit comprising:
disposing a transistor coupled between a first rail and a second rail of the integrated circuit; and
inducing a parasitic current within the transistor responsive to an ESD event occurring on one of the first and second rails by limiting a gate turn on voltage to the transistor to a voltage selected to maximize the parasitic current, wherein inducing a parasitic current within the transistor comprises limiting a turn on voltage applied to a gate of the transistor to less than a full turn on voltage for the transistor.
7. The method of claim 6 , wherein the first rail has a voltage, Vdd, wherein Vdd is 2.5 volts (V), and the method comprises limiting the turn on voltage to 1V or less.
8. A method of providing electrostatic discharge (ESD) protection in an integrated circuit, the integrated circuit including a transistor coupled between a first rail and a second rail of the integrated circuit, the method comprising:
providing a voltage limited gate turn-on voltage to a gate of the transistor responsive to an ESD events, and
inducing a maximized parasitic current between the first rail and the second rail within a parasitic bipolar transistor component of the transistor, wherein providing the voltage limited gate turn-on voltage to the gate comprises limiting a turn on voltage applied to the gate to less than a full turn on voltage for the transistor.