Tunneling transistor

1. A device comprising:

a substrate; and

a fin-type transistor disposed on the substrate, wherein the transistor comprises a fin structure which serves as a body of the transistor, wherein the fin structure includes first and second end regions and an intermediate region in between the first and second end regions of the fin structure,

a source region disposed on the first end region, a drain region disposed in the second end region and a gate disposed on the intermediate region of the fin structure,

a fin buffer layer disposed in the source region of the fin structure and a source layer over the fin buffer layer, and

a channel region disposed adjacent to the source region and a gate dielectric of the gate, wherein a source tunneling junction is aligned to the gate with a controlled channel thickness T CH .

2. The device of claim 1 wherein the fin buffer layer is a conformal fin buffer layer and the source layer is a conformal source layer over the fin buffer layer.

3. The device of claim 2 wherein the fin buffer and the source layers are epitaxial crystalline semiconductor layers.

4. The device of claim 3 wherein a top surface of the source region is elevated above a top surface of the drain region.

5. The device of claim 1 wherein the channel region includes a channel layer having an epitaxial crystalline semiconductor layer.

6. A method for forming a device comprising:

providing a substrate; and

forming a fin-type transistor on the substrate, wherein forming the transistor comprises

forming a fin structure having a shape, wherein the fin structure includes first and second end regions and an intermediate region in between the first and second end regions of the fin structure and the fin structure serves as a body of the transistor,

forming a source region on the first end region, a drain region in the second end region and agate on the intermediate region of the fin structure,

forming a fin buffer layer in the source region over the fin structure and a source layer over the fin buffer layer, and

forming a channel region adjacent to the source region and a gate dielectric of the gate, wherein a source tunneling junction is aligned to the gate with a controlled channel thickness T CH .

7. The method of claim 6 wherein the shape of the fin structure comprises first and second fins defined in the first end and intermediate regions and a common fin defined in the second end region of the fin structure.

8. The method of claim 7 wherein forming the fin structure comprises:

providing a first hard mask layer over a top surface of the substrate; and

patterning the first hard mask layer to correspond to the shape of the fin structure.

9. The method of claim 8 further comprises:

forming a dummy gate on the substrate, wherein the dummy gate traverses the intermediate region of the fin structure; and

removing portions of the first patterned hard mask which are unprotected by the dummy gate.

10. The method of claim 9 wherein forming the drain region comprises:

providing a patterned mask layer which covers the substrate, the first end region of the fin structure and the dummy gate while exposing the second end region of the fin structure; and

implanting second polarity type dopants into the second end region of the fin structure.

11. The method of claim 9 wherein forming the source region comprises:

providing a second patterned hard mask which covers the drain region and the dummy gate while exposing the first and second fins in the first end region;

forming a first semiconductor layer which serves as the buffer layer over each of the fins; and

forming a second semiconductor layer which serves as the source layer over the buffer layers.

12. The method of claim 11 wherein the first and second semiconductor layers are formed by selective epitaxial growth.

13. The method of claim 11 further comprises:

implanting first polarity type dopants into the source layer; and

removing the second patterned hard mask.

14. The method of claim 13 further comprises:

providing an interlevel dielectric layer over the substrate; and

removing the dummy gate and the first patterned hard mask under the dummy gate, wherein removal of the dummy gate and the first patterned hard mask forms an opening which exposes sides of the source and buffer layers and the intermediate region of the fin structure.

15. The method of claim 14 wherein forming the channel region comprises forming a third semiconductor layer which serves as a channel layer on exposed sides of the source and buffer layers and the intermediate region of the fin structure.

16. The method of claim 15 wherein the third semiconductor layer is formed by selective epitaxial growth.

17. The method of claim 13 further comprises:

removing the dummy gate and the first patterned hard mask under the dummy gate, wherein removal of the dummy gate and the first patterned hard mask exposes sides of the source and buffer layers and the intermediate and drain regions of the fin structure.

18. The method of claim 17 wherein forming the channel region comprises forming a third semiconductor layer which serves as a channel layer on exposed sides of the source and buffer layers and the intermediate and drain regions of the fin structure.

19. The method of claim 18 wherein the third semiconductor layer is formed by selective epitaxial growth.

20. The method of claim 6 further comprises forming sidewall spacers on sidewalls of the gate.