IP Library Granted Patent US 8,785,287
Granted Patent B2
US 8,785,287 · App. 12/803,754 · Granted Jul 22, 2014

Method to tune narrow width effect with raised S/D structure

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Quick Facts
Patent No.
US 8,785,287
App. No.
12/803,754
Granted
Jul 22, 2014
Kind
B2
Abstract

A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width.

Claims (17)

1. A method for forming a semiconductor device, the method comprising:

providing a substrate of a first conductivity type;

forming thereon a field effect transistor (FET) structure including a gate, said gate having a gate width, a first raised source/drain (S/D) region and a second raised S/D region, the first and second raised S/D regions of a second conductivity type;

forming a halo region by implanting dopants of the first conductivity type within the substrate, wherein forming the halo region further comprises, implanting first dopants of the first conductivity type at a first predetermined tilt angle and at a first predetermined twist angle substantially equal to zero degrees relative to a direction perpendicular to the gate width to form a first portion of the halo region and implanting second dopants of the first conductivity type at a second predetermined tilt angle and at a second predetermined twist angle to form a second portion of the halo region, such that a doping concentration at a given depth below a channel surface near a center of the first raised S/D region is lower than a doping concentration at the given depth below the channel surface near an edge of the first raised S/D region.

2. The method in accordance with claim 1 wherein the second predetermined twist angle is between about 20 and 70 degrees.

3. The method in accordance with claim 2 wherein the second predetermined twist angle is about 45 degrees.

4. The method in accordance with claim 1 wherein the first predetermined tilt angle is equal to the second predetermined tilt angle.

5. The method in accordance with claim 4 wherein the second predetermined twist angle is between about 20 and 70 degrees.

6. A method for forming a field-effect transistor (FET) for increasing a gate threshold of the field effect transistor, the method comprising:

providing a substrate of a first conductivity type;

forming thereon a FET structure including a gate, said gate having a gate width, a first raised source/drain (S/D) region and a second raised S/D region, the first and second raised S/D regions of a second conductivity type;

implanting at a first predetermined tilt angle and at a first predetermined twist angle substantially equal to zero degrees relative to a direction perpendicular to the gate width dopants of the first conductivity type within the substrate to form an intermediate halo region;

implanting at a second predetermined tilt angle and at a second predetermined twist angle of between about 20 and 70 degrees dopants of the first conductivity type to form a final halo region including the intermediate halo region.

7. The method in accordance with claim 6 wherein a doping concentration at a predetermined depth below a channel surface near a center of the first raised S/D region is lower than a doping concentration at the predetermined depth near an edge of the first raised S/D region.

8. The method in accordance with claim 6 wherein the second predetermined twist angle is about 45 degrees.

9. The method in accordance with claim 6 wherein the first predetermined tilt angle is equal to the second predetermined tilt angle.

10. The method in accordance with claim 6 wherein the raised S/D regions are at least partially surrounded by a shallow trench isolation structure.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 19, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Reel/Frame 054481/0673 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 19, 2020
From: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 054600/0031 →
RELEASE OF SECURITY INTEREST Recorded Nov 18, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054475/0718 →
SECURITY AGREEMENT Recorded Nov 27, 2018
From: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 047660/0203 →