Granted Patent B2

US 8,293,546 · App. 12/477,448 · Granted Oct 23, 2012

Abstract

Claims (30)

1. A method of manufacture of an integrated circuit comprising:

forming reticle pattern having at least a first shape and a second shape for fabricating an integrated circuit from the reticle pattern;

detecting a sub-geometry, a singularity, or a combination thereof in the reticle pattern between the first shape and the second shape;

applying a unit cell, a patch cell, or a combination thereof to the reticle pattern for removing the sub-geometry, the singularity, or the combination thereof from the reticle pattern including forming a new shape by performing a Boolean operation on the first shape, the second shape, the unit cell, the patch cell, or the combination thereof; and

fabricating the integrated circuit from the reticle pattern having at least the first shape, the second shape, and including the new shapes on the integrated circuit.

2. The method as claimed in claim 1 further comprising setting a width and a height of the unit cell based on the sub-geometry size.

3. The method as claimed in claim 1 wherein applying the patch cell includes:

bridging lines between rectangular shapes; and

intersecting, a measurement from the singularity, the lines and the rectangular shapes.

4. The method as claimed in claim 1 wherein fabricating the integrated circuit includes:

providing a substrate;

coating a photoresist material on the substrate;

focusing a set of projection optics on the photoresist material; and

providing a reticle system for projecting the reticle pattern.

5. The method as claimed in claim 1 wherein detecting the singularity includes locating two rectangular shapes meeting at a corner.

6. A method of manufacture of an integrated circuit system comprising:

forming reticle data having a first shape and a second shape;

detecting a sub-geometry, a singularity, or a combination thereof in the reticle data including locating vertices of the first shape and the second shape;

applying a unit cell, a patch cell, or a combination thereof for removing the sub-geometry, the singularity, or the combination thereof from the reticle data including forming a new shape by performing a Boolean operation on the first shape, the second shape, the unit cell, the patch cell, or the combination thereof; and

fabricating an integrated circuit from the reticle data including forming the new shapes on the integrated circuit.

7. The method as claimed in claim 6 further comprising setting a width and a height of the unit cell based on the sub-geometry size including providing a tab measurement having a fixed value.

8. The method as claimed in claim 6 wherein applying the patch cell includes:

bridging lines between rectangular shapes including forming the lines parallel to each other; and

intersecting, a measurement from the singularity, the lines and the rectangular shapes including forming a bridge region between the rectangular shapes.

9. The method as claimed in claim 6 wherein fabricating the integrated circuit includes:

providing a substrate including providing a stepper for mounting the substrate;

coating a photoresist material on the substrate including applying a super fine pattern forming material;

focusing a set of projection optics on the photoresist material including converging radiation beams; and

providing a reticle system for projecting the reticle data for forming the integrated circuit layer by layer.

10. The method as claimed in claim 6 wherein detecting the singularity includes locating two rectangular shapes meeting at a corner including failing a mask rules check.

Assignments (6)