Memory cell with improved retention

1. A method for forming a semiconductor device comprising:

providing a substrate prepared with a second gate feature having side and top surfaces;

forming a first gate dielectric layer having first and second sub-layers over the second gate feature and substrate;

processing the first gate dielectric layer to form nano-crystals in first and third portions of the first gate dielectric layer over the top surface of the second gate feature and substrate while a second portion on the side surfaces of the second gate feature are devoid of nano-crystals, wherein the first and third portions of the second sub-layer of the first gate dielectric layer are formed with a sufficient thickness to form nano-crystals when subsequently processed, and the second portion of the second sub-layer of the first gate dielectric layer is formed with a thickness insufficient to form nano-crystals when subsequently processed;

forming a first gate electrode layer over the substrate; and

patterning the first gate electrode layer, first gate dielectric layer and second gate feature to form a memory cell with a split gate.

2. The method of claim 1 wherein the memory cell comprises a non-volatile memory cell.

3. The method of claim 1 wherein the first gate dielectric layer comprises silicon or germanium nano-crystals.

4. The method of claim 1 wherein the first sub-layer of the first gate dielectric layer comprises silicon oxide.

5. The method of claim 1 wherein the second sub-layer of the first gate dielectric layer is processed to form nano-crystals in the first and third portions while its second portion is fully consumed.

6. The method of claim 1 wherein the formation of the first gate dielectric layer comprises a PVD process.

7. The method of claim 5 wherein the formation of the nano-crystals comprises oxidation.

8. The method of claim 5 wherein the full consumption of the second portion of the first gate dielectric layer comprises oxidation, wet etch, or a combination thereof.

9. A method for forming a device comprising:

providing a substrate prepared with a feature having top and side surfaces; and

forming a continuous device layer on the top and side surfaces of the feature and a top surface of the substrate;

processing the continuous device layer to form nano-crystals along first and third portions of the device layer over the top surface of the feature and the substrate and a second portion over the side surface of the feature is devoid of nano-crystals, wherein

the first and third portions of the device layer are formed with a sufficient thickness to form nano-crystals when subsequently processed; and

the second portion of the device layer is formed with a thickness insufficient to form nano-crystals when subsequently processed.

10. The method of claim 9 wherein the device comprises a memory cell with a split gate.

11. The method of claim 9 wherein the device layer comprises silicon or germanium nano-crystals.

12. The method of claim 9 wherein the second portion of the device layer is fully consumed.

13. The method of claim 9 wherein the device layer comprises first and second sub-layers.

14. The method of claim 10 wherein the device layer comprises a gate dielectric layer.

15. The method of claim 13 wherein the formation of the nano-crystals comprises oxidation.

16. The method of claim 15 wherein the second portion of the device layer is fully consumed.

17. A method of forming a device comprising:

providing a substrate prepared with a feature having top and side surfaces; and

forming a continuous device layer covering the top and side surfaces of the feature and a top surface of the substrate;

forming a spacer on a second portion of the device layer over the side surface of the feature; and

processing the continuous device layer to form nano-crystals in first and third portions of the device layer over the top surfaces of the feature and the substrate, wherein the spacer prevents formation of nano-crystals in the second portion of the device layer over the side surface of the feature during processing of the continuous device layer.

18. A device comprising:

a feature disposed on a substrate having top and side surfaces; and

a continuous device layer on the top and side surfaces of the feature and a top surface of the substrate, wherein horizontal portions of the device layer disposed over the top surface of the feature and the substrate comprise nano-crystals throughout the horizontal portions along a plane of the substrate and a non-horizontal portion over the side surface of the feature is devoid of nano-crystals, wherein the continuous device layer is a non-conformal layer with the horizontal portions having a thickness greater than the non-horizontal portion.

19. A method for forming a semiconductor device comprising:

providing a substrate prepared with a second gate feature having side and top surfaces;

depositing a first gate dielectric layer over the second gate feature and substrate;

processing the as-deposited first gate dielectric layer to form nano-crystals in first and third portions of the first gate dielectric layer over the top surface of the second gate feature and substrate while not forming nano-crystals in a second portion of the first gate dielectric layer on the side surfaces of the second gate feature;

forming a first gate electrode layer over the substrate; and

patterning the first gate electrode layer, first gate dielectric layer and second gate feature to form a memory cell with a split gate.

20. The method of claim 19 wherein:

the first and third portions of the first gate dielectric layer are formed with a sufficient thickness to form nano-crystals when subsequently processed; and

the second portion of the first gate dielectric layer is formed with a thickness insufficient to form nano-crystals when subsequently processed.

21. The method of claim 19 comprising:

forming a spacer on the second portion of the first gate dielectric layer over the side surface of the second gate feature, wherein the spacer prevents formation of nano-crystals in the second portion of the first gate dielectric layer during processing of the as-deposited first gate dielectric layer.