Integrated circuit system with sub-geometry removal and method of manufacture thereof
View Patent ↗A method of manufacture of an integrated circuit system includes: forming reticle data; detecting a sub-geometry, a singularity, or a combination thereof in the reticle data; applying a unit cell, a patch cell, or a combination thereof for removing the sub-geometry, the singularity, or the combination thereof from the reticle data; and fabricating an integrated circuit from the reticle data.
1. An integrated circuit comprising:
a first circuit layer, in a reticle pattern, having at least a first shape and a second shape connected by a unit cell, a patch cell, or a combination thereof from the reticle pattern for removing a sub-geometry, a singularity, or a combination thereof from the reticle pattern, the first shape and the second shape having vertices located to detect the sub-geometry, the singularity, or a combination thereof, the first circuit layer having a new shape formed by a Boolean operation on the first shape, the second shape, the unit cell, the patch cell, or a combination thereof includes new shapes formed on the integrated circuit, the patch cell includes lines, between rectangular shapes, spaced a measurement from the singularity on the reticle pattern includes a bridge region between the rectangular shapes; and
at least a second circuit layer for forming a device.
2. The integrated circuit as claimed in claim 1 further comprising a width and a height of the unit cell based on the sub-geometry size.
3. The integrated circuit as claimed in claim 1 wherein the patch cell includes lines, between rectangular shapes, spaced a measurement from the singularity on the reticle pattern.
4. The integrated circuit as claimed in claim 1 further comprising a substrate having the reticle pattern formed thereon.
5. The integrated circuit as claimed in claim 1 wherein the singularity includes two rectangular shapes with a corner collocated.
6. The integrated circuit as claimed in claim 1 further comprising a width and a height of the unit cell based on the sub-geometry size includes a tab measurement with a fixed value.
7. The integrated circuit as claimed in claim 1 wherein the integrated circuit includes a substrate having the reticle pattern formed thereon includes the integrated circuit diced from the substrate.
8. The integrated circuit as claimed in claim 1 wherein the singularity includes two rectangular shapes with a corner collocated including determining a single point of contact of the rectangular shapes.