RRAM cell with bottom electrode(s) positioned in a semiconductor substrate
View Patent ↗Generally, the subject matter disclosed herein relates to the fabrication of an RRAM cell using CMOS compatible processes. A resistance random access memory device is disclosed which includes a semiconducting substrate, a top electrode, at least one metal silicide bottom electrode formed at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below the top electrode, and at least one insulating layer positioned between the top electrode and at least a portion of the at least one bottom electrode. A method of making a resistance random access memory device is disclosed that includes forming an isolation structure in a semiconducting substrate to thereby define an enclosed area, performing at least one ion implantation process to implant dopant atoms into the substrate within the enclosed area, after performing the at least one ion implantation process, forming a layer of refractory metal above at least portions of the substrate, and performing at least one heat treatment process to form at least one metal silicide bottom electrode at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below at least a portion of a top electrode of the device.
1. A resistance random access memory device, comprising:
a semiconducting substrate;
a metal silicide top electrode positioned above said substrate;
a single metal silicide bottom electrode formed at least partially in said substrate, wherein at least a portion of said single bottom electrode is positioned below an entire width of said top electrode; and
at least one insulating layer positioned between said top electrode and said single bottom electrode, wherein the at least one layer of insulating material is adapted to breakdown when an operating voltage is applied to said top electrode so as to thereby allow formation of at least one conductive path that extends through said at least one layer of insulating material between said metal silicide top electrode and said single metal silicide bottom electrode.
2. The device of claim 1 , wherein said top electrode and said single bottom electrode are made of the same metal silicide material.
3. The device of claim 1 , wherein said top electrode and said single bottom electrode are made of different metal silicide materials.
4. The device of claim 1 , wherein said single bottom electrode is bounded by an isolation structure positioned in said substrate that surrounds said device.
5. The device of claim 1 , wherein said at least one layer of insulating material comprises:
a first layer of insulating material positioned on said substrate, said first layer of insulating material being a silicon-rich SiO x material; and
a second layer of insulating material positioned on said first layer of insulating material, said second layer of insulating material having a dielectric constant of 3.9 or greater, wherein said top electrode is positioned on said second layer of insulating material.
6. A resistance random access memory device, comprising:
a semiconducting substrate;
a metal silicide top electrode positioned above said substrate;
two separated metal silicide bottom electrodes formed at least partially in said substrate, wherein a portion of each of said two bottom electrodes is positioned below separate portions of said top electrode; and
at least one insulating layer positioned between said portions of said top electrode and said underlying portions of said two bottom electrodes, wherein the at least one layer of insulating material is adapted to breakdown when an operating voltage is applied to said top electrode so as to thereby allow formation of at least one conductive path that extends through said at least one layer of insulating material between said metal silicide top electrode and at least one of said two separated metal silicide bottom electrodes, said at least one layer of insulating material comprising:
a first layer of insulating material positioned on said substrate, said first layer of insulating material being a silicon-rich SiO x material; and
a second layer of insulating material positioned on said first layer of insulating material, said second layer of insulating material having a dielectric constant of 3.9 or greater, wherein said top electrode is positioned on said second layer of insulating material.
7. The device of claim 6 , wherein said top electrode and said two separated bottom electrodes are made of the same metal silicide material.
8. The device of claim 6 , wherein said top electrode and said two separated bottom electrodes are made of different metal silicide materials.
9. The device of claim 6 , wherein said top electrode and each of said two separated bottom electrodes are made of nickel silicide.
10. The device of claim 6 , wherein said two bottom electrodes are bounded by an isolation structure positioned in said substrate that surrounds said device.
11. The device of claim 6 , wherein said at least one insulating layer is comprised of a single layer of a high-k dielectric material having a dielectric constant of 3.9 or greater.
12. An array of resistance random access memory device, comprising:
a semiconducting substrate;
at least four spaced apart metal silicide bottom electrodes formed at least partially in said substrate; and
a common metal silicide top electrode structure that vertically overlaps a vertically underlying portion of each of said at least four spaced apart metal silicide bottom electrodes;
at least one insulating layer positioned between said overlapping portions of said top electrode and said vertically underlying portions of said at least four spaced apart metal silicide bottom electrodes, wherein the at least one layer of insulating material is adapted to breakdown when an operating voltage is applied to said common top electrode so as to thereby allow formation of at least one conductive path that extends through said at least one layer of insulating material between said common metal silicide top electrode and one of said at least four spaced apart metal silicide bottom electrodes, said at least one layer of insulating material comprising:
a first layer of insulating material positioned on said substrate, said first layer of insulating material being a silicon-rich SiO x material; and
a second layer of insulating material positioned on said first layer of insulating material, said second layer of insulating material having a dielectric constant of 3.9 or greater, wherein said common top electrode is positioned on said second layer of insulating material.
13. The array of claim 12 , wherein said memory array consists of four spaced apart metal silicide bottom electrodes and said memory array defines a 2×2 memory cell.
14. The array of claim 12 , wherein said memory array consists of six spaced apart metal silicide bottom electrodes and said memory array defines 2×3 memory cell.
15. The array of claim 12 , wherein said memory array consists of nine spaced apart metal silicide bottom electrodes and said memory array defines a 3×3 memory cell.
16. The array of claim 12 , further comprising circuitry means for selectively grounding only one of said at least four spaced apart metal silicide bottom electrodes when said operating voltage is applied to said common top electrode.
17. The device of claim 12 , wherein said common top electrode and said at least four spaced apart metal silicide bottom electrodes are made of the same metal silicide material.
18. The device of claim 12 , wherein said common top electrode and said at least four spaced apart metal silicide bottom electrodes are made of different metal silicide materials.
19. The device of claim 12 , wherein said common top electrode and each of said at least four spaced apart metal silicide bottom electrodes are made of nickel silicide.
20. The device of claim 12 , wherein said at least one insulating layer is comprised of a single layer of a high-k dielectric material having a dielectric constant of 3.9 or greater.