Methods for fabricating integrated circuits using chemical mechanical polishing
View Patent ↗Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon material layer over a semiconductor substrate. The semiconductor substrate includes a logic device region and a memory array region. The memory array region has a memory device formed on the semiconductor substrate. The method further includes forming a capping layer over the silicon material layer and over the memory device and removing the capping layer from over the memory device in the memory array region using a first chemical mechanical polishing process while leaving at least a first portion of the capping layer in place over the logic device region. Further, the method includes removing the first the silicon material layer from over the memory device in the memory array region using a second chemical mechanical polishing process.
1. A method for fabricating an integrated circuit comprising:
forming a silicon material layer over a semiconductor substrate, the semiconductor substrate including a logic device region and a memory array region, the memory array region having formed on the semiconductor substrate a memory device;
forming a capping layer over the silicon material layer and over the memory device;
removing the capping layer from over the memory device in the memory array region using a first chemical mechanical polishing process while leaving at least a first portion of the capping layer in place over the logic device region; and
removing the first silicon material layer from over the memory device in the memory array region using a second chemical mechanical polishing process while leaving at least a second portion of the capping layer in place over the logic device region, the at least a second portion having a thickness that is less than the at least a first portion.
2. The method of claim 1 , wherein forming the silicon material layer over the semiconductor substrate comprises forming a polycrystalline silicon material layer over the semiconductor substrate.
3. The method of claim 1 , wherein forming the capping layer over the silicon material comprises forming a silicon oxide capping layer over the silicon material.
4. The method of claim 1 , wherein performing the first chemical mechanical polishing process comprises applying a hard pad to the semiconductor substrate.
5. The method of claim 4 , wherein performing the first chemical mechanical polishing process comprises applying a slurry having a selectivity on the basis of polysilicon:silicon oxide:silicon nitride of about 200 to about 300:1:1.
6. The method of claim 1 , wherein performing the first chemical mechanical polishing process comprises applying a slurry having a selectivity on the basis of polysilicon:silicon oxide:silicon nitride of about 200 to about 300:1:1.
7. The method of claim 1 , wherein performing the second chemical mechanical polishing process comprises applying a soft pad to the semiconductor substrate.
8. The method of claim 7 , wherein performing the second chemical mechanical polishing process comprises applying a slurry having a selectivity on the basis of polysilicon:silicon oxide:silicon nitride of about 500:1:1.
9. The method of claim 1 , wherein performing the second chemical mechanical polishing process comprises applying a slurry having a selectivity on the basis of polysilicon:silicon oxide:silicon nitride of about 500:1:1.
10. The method of claim 1 , wherein the logic device region and the memory array region are formed on a single layout block of the integrated circuit.
11. The method of claim 1 , further comprising removing the at least a second portion of the capping layer from over the first silicon material layer in the logic device region.
12. The method of claim 11 , wherein removing the at least a second portion of the capping layer from over the first silicon material layer comprises applying a dilute HF wet etch.
13. The method of claim 1 , wherein performing the first chemical mechanical polishing process comprises applying a slurry having a selectivity on the basis of polysilicon:silicon oxide:silicon nitride of about 200 to about 300:1:1 and wherein performing the second chemical mechanical polishing process comprises applying a slurry having a selectivity on the basis of polysilicon:silicon oxide:silicon nitride of about 500:1:1.
14. A method for fabricating an integrated circuit comprising:
forming a silicon material layer over a semiconductor substrate, the semiconductor substrate including a logic device region and a memory array region, the memory array region having formed on the semiconductor substrate a memory device;
forming a capping layer over the silicon material layer and over the memory device;
removing the capping layer from over the memory device in the memory array region using a first chemical mechanical polishing process while leaving at least a first portion of the capping layer in place over the logic device region, wherein performing the first chemical mechanical polishing process comprises applying a hard pad to the semiconductor substrate; and
removing the first silicon material layer from over the memory device in the memory array region using a second chemical mechanical polishing process while leaving at least a second portion of the capping layer in place over the logic device region, the at least a second portion having a thickness that is less than the at least a first portion, wherein performing the second chemical mechanical polishing process comprises applying a soft pad to the semiconductor substrate.
15. The method of claim 14 , wherein forming the silicon material layer over the semiconductor substrate comprises forming a polycrystalline silicon material layer over the semiconductor substrate.
16. The method of claim 14 , wherein forming the capping layer over the silicon material comprises forming a silicon oxide capping layer over the silicon material.
17. The method of claim 14 , further comprising removing the at least a second portion of the capping layer from over the first silicon material layer in the logic device region by applying a dilute HF wet etch.