Methods for fabricating integrated circuits with low, medium, and/or high voltage transistors on an extremely thin silicon-on-insulator substrate

1. A method for fabricating an integrated circuit comprising:

providing or obtaining an extremely thin silicon-on-insulator (ETSOI) substrate;

dividing the ETSOI substrate into a low voltage field effect transistor (FET) region and a medium voltage FET region; and

forming a low voltage FET within the low voltage FET region, and forming a medium voltage FET within the medium voltage FET region,

wherein, channel, source, and drain structures of the low voltage FET are formed in an upper silicon layer of the ETSOI substrate that is disposed above a buried oxide layer of the ETSOI substrate,

wherein channel, source, and drain structures of the medium voltage FET are formed at least partially below the upper silicon layer, and wherein:

the ETSOI substrate comprises a silicon base layer, the buried oxide (BOX) insulating layer, which is disposed over and in contact with the silicon base layer, and the upper silicon layer, which is disposed over and in contact with the BOX insulating layer, wherein the upper silicon layer has a thickness above the BOX insulating layer of about 3 nm to about 20 nm; and

forming the low and medium voltage FETs comprises:

forming a plurality of first shallow trench isolation (STI) structures in the ETSOI substrate, the first STI structures dividing the ETSOI substrate into a low voltage field effect transistor (FET) region and a medium voltage FET region;

forming first and second masking layer segments over the ETSOI substrate, the first masking layer segment comprising a segment formed over an entirety of the low voltage FET region, the second masking layer segment comprising two spaced apart segments formed over the medium voltage FET region;

removing portions of the upper silicon layer and the BOX insulating layer that are not beneath the first and second masking layer segments, thereby forming two first stacks comprising segments of the BOX insulating layer and the upper silicon layer in the medium voltage FET region;

forming a polycrystalline silicon layer within the medium voltage FET region between and adjacent to the two first stacks, the polycrystalline silicon layer being formed to a height commensurate with the upper silicon layer;

removing the first and second masking layer segments from over the ETSOI substrate;

forming source and drain ion implant regions within the medium voltage FET region, wherein forming the source and drain ion implant regions in the medium voltage FET region comprises forming the source and drain ion implant regions adjacent to and underneath the two first stacks;

oxidizing the segments of the upper silicon layer in the two first stacks;

masking the medium FET region while forming a first gate electrode structure over the low voltage FET region, thereby forming a low voltage FET over the ETSOI; and

un-masking the medium voltage FET region then forming a second gate structure over the medium voltage FET region, thereby forming a medium voltage FET over the ETSOI.

2. The method of claim 1 , wherein the medium voltage FET region comprises a doped band formed below the channel, source, and drain structures of the medium voltage FET.

3. The method of claim 1 , wherein the low voltage FET region comprises a doped band formed below the channel, source, and drain structures of the low voltage FET.

4. The method of claim 1 , wherein the first and second masking layer segments comprise silicon nitride.

5. The method of claim 1 , wherein the step of masking comprises masking with a silicon dioxide material.

6. The method of claim 1 , wherein the silicon base layer comprises p-type silicon and the source and drain ion implant regions of both the low and medium voltage FETs comprise n-type silicon, or wherein the silicon base layer comprises n-type silicon and the source and drain ion implant regions of both the low and medium voltage FETs comprise p-type silicon.

7. A method for fabricating an integrated circuit comprising:

providing or obtaining an extremely thin silicon-on-insulator (ETSOI) substrate;

dividing the ETSOI substrate into a low voltage field effect transistor (FET) region and a high voltage FET region; and

forming a low voltage FET within the low voltage FET region and forming a high voltage FET within the high voltage FET voltage region,

wherein, channel, source, and drain structures of the low voltage FET are formed in an upper silicon layer of the ETSOI substrate that is disposed above a buried oxide layer of the ETSOI substrate,

wherein channel, source, and drain structures of the high voltage FET are formed at least partially below the upper silicon layer, and wherein:

the ETSOI substrate comprises a silicon base layer, the buried oxide (BOX) insulating layer, which is disposed over and in contact with the silicon base layer, and the upper silicon layer, which is disposed over and in contact with the BOX insulating layer, wherein the upper silicon layer has a thickness above the BOX insulating layer of about 3 nm to about 20 nm; and

forming the low and high voltage FETs comprises:

forming a plurality of first shallow trench isolation (STI) structures in the ETSOI substrate, the first STI structures dividing the ETSOI substrate into a low voltage field effect transistor (FET) region and a high voltage FET region, and forming two second STI structures within the high voltage FET region;

forming first and second masking layer segments over the ETSOI substrate, the first masking layer segment comprising a segment formed over an entirety of the low voltage FET region, the second masking layer segment comprising a segment formed between the two second STI structures in the high voltage FET region;

removing portions of the upper silicon layer and the BOX insulating layer that are not beneath the first and second masking layer segments, thereby forming a first stack comprising a segment of the BOX insulating layer and the upper silicon layer in the high voltage FET region and between the two second STI structures;

forming a polycrystalline silicon layer within the high voltage region adjacent to the second stack, the polycrystalline silicon layer being formed to a height commensurate with the upper silicon layer;

removing the first and second masking layer segments from over the ETSOI substrate;

forming source and drain ion implant regions within the high voltage FET region, wherein forming the source and drain ion implant regions in the high voltage FET region comprises forming the source and drain ion implant regions adjacent to and underneath the two second STI structures;

oxidizing the segment of the upper silicon layer in the first stack;

masking the high voltage FET region while forming a first gate electrode structure over the low voltage FET region, thereby forming a low voltage FET over the ETSOI; and

un-masking the high voltage FET region then forming a second gate structure over the high voltage FET region, thereby forming a high voltage FET over the ETSOI.

8. The method of claim 7 , wherein the high voltage FET region comprises a channel formed beneath the BOX insulating layer.

9. The method of claim 7 , wherein the low voltage FET region comprises a doped band formed below the channel, source, and drain structures of the medium voltage FET.

10. The method of claim 7 , wherein the first and second masking layer segments comprise silicon nitride.

11. The method of claim 7 , wherein the step of masking comprises masking with a silicon dioxide material.

12. The method of claim 7 , wherein the silicon base layer comprises p-type silicon and the source and drain ion implant regions of both the low and high voltage FETs comprise n-type silicon.

13. A method for fabricating an integrated circuit comprising:

providing or obtaining an extremely thin silicon-on-insulator (ETSOI) substrate;

dividing the ETSOI substrate into a low voltage field effect transistor (FET) region, a medium voltage FET region, and a high voltage FET region; and

forming a low voltage FET within the low voltage FET region, forming a medium voltage FET within the medium voltage FET region, and forming a high voltage FET within the high voltage FET voltage region,

wherein, channel, source, and drain structures of the low voltage FET are formed in an upper silicon layer of the ETSOI substrate that is disposed above a buried oxide layer of the ETSOI substrate,

wherein channel, source, and drain structures of the medium and high voltage FETs are formed at least partially below the upper silicon layer, and wherein:

the ETSOI substrate comprises a silicon base layer, the buried oxide (BOX) insulating layer, which is disposed over and in contact with the silicon base layer, and the upper silicon layer, which is disposed over and in contact with the BOX insulating layer, wherein the upper silicon layer has a thickness above the BOX insulating layer of about 3 nm to about 20 nm; and

forming the low, medium, and high voltage FETs comprises:

forming a plurality of first shallow trench isolation (STI) structures in the ETSOI substrate, the STI structures dividing the ETSOI substrate into a low voltage field effect transistor (FET) region, a medium voltage FET region, and a high voltage FET region, and forming two second STI structures within the high voltage FET region;

forming first, second, and third masking layer segments over the ETSOI substrate, the first masking layer segment comprising a segment formed over an entirety of the low voltage FET region, the second masking layer segment comprising two spaced apart segments formed over the medium voltage FET region, the third masking layer segment comprising a segment formed between the two second STI structures in the high voltage FET region;

removing portions of the upper silicon layer and the BOX insulating layer that are not beneath the first, second, and third masking layer segments, thereby forming two first stacks comprising segments of the BOX insulating layer and the upper silicon layer in the medium voltage FET region and a second stack comprising a segment of the BOX insulating layer and the upper silicon layer in the high voltage FET region and between the two second STI structures;

forming a polycrystalline silicon layer within the medium voltage FET region between and adjacent to the two first stacks and within the high voltage region adjacent to the second stack, the polycrystalline silicon layer being formed to a height commensurate with the upper silicon layer;

removing the first, second, and third masking layer segments from over the ETSOI substrate;

forming source and drain ion implant regions within the medium voltage FET region and the high voltage FET region, wherein forming the source and drain ion implant regions in the medium voltage FET region comprises forming the source and drain ion implant regions adjacent to and underneath the two first stacks, and wherein forming the source and drain ion implant regions in the high voltage FET region comprises forming the source and drain ion implant regions adjacent to and underneath the two second STI structures;

oxidizing the segments of the upper silicon layer in the two first stacks and oxidizing the segment of the upper silicon layer in the second stack;

masking the medium and high voltage FET regions while forming a first gate electrode structure over the low voltage FET region, thereby forming a low voltage FET over the ETSOI; and

un-masking the medium and high voltage FET regions then forming second and third gate structures over the medium and high voltage FET regions, respectively, thereby forming medium and high voltage FETs over the ETSOI.

14. The method of claim 13 , wherein the medium voltage FET region comprises a doped band formed below the channel, source, and drain structures of the medium voltage FET and wherein the high voltage FET region comprises a channel formed beneath the BOX insulating layer.

15. The method of claim 13 , wherein the low voltage FET region comprises a channel formed beneath the BOX insulating layer.

16. The method of claim 13 , wherein the first, second, and third masking layer segments comprise silicon nitride.

17. The method of claim 13 , wherein the silicon base layer comprises p-type silicon and the source and drain ion implant regions of both the low, medium, and high voltage FETs comprise n-type silicon, or wherein the silicon base layer comprises n-type silicon and the source and drain ion implant regions of both the low, medium, and high voltage FETs comprise p-type silicon.