Method for reducing silicide defects in integrated circuits
View Patent ↗A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.
1. A method for forming a transistor in an integrated circuit (IC) comprising:
providing a substrate having a gate on the substrate, the gate having gate sidewalls, and diffusion regions in the substrate adjacent to the gate;
forming dielectric spacers on the gate sidewalls;
forming metal silicide contacts over the diffusion regions, wherein portions of the metal silicide contacts are covered by the spacers; and
pulling back the dielectric spacers, wherein outer walls of the dielectric spacers are aligned with edges of the metal silicide contacts to reduce stress on the metal silicide contacts.
2. The method of claim 1 wherein forming the metal silicide contacts comprises performing first and second annealing processes.
3. The method of claim 1 wherein pulling back the dielectric spacers comprises an anisotropic etch.
4. The method of claim 1 wherein forming the metal silicide contacts comprises performing first and second annealing processes.
5. The method of claim 4 wherein pulling back the dielectric spacers is performed between the first and second annealing processes.
6. The method of claim 5 wherein pulling back the dielectric spacers comprises an anisotropic etch.
7. The method of claim 1 comprises:
cleaning the substrate surface after forming the dielectric spacers, the cleaning forms undercut regions in a lower portion of the dielectric spacers such that edge portions of the metal silicide contacts are disposed in the undercut regions; and
pulling back the dielectric spacers after metal silicide contacts are formed to align the outer walls of the dielectric spacers with edges of the metal silicide contacts.
8. The method of claim 7 wherein pulling back the dielectric spacers comprises an anisotropic etch.
9. The method of claim 8 wherein forming the metal silicide contacts comprises performing first and second annealing processes.
10. The method of claim 9 wherein pulling back the dielectric spacers is performed between the first and second annealing processes.
11. The method of claim 1 wherein the metal silicide contacts comprise nickel or nickel alloy.
12. A method for reducing metal pipes comprising:
providing a feature on a substrate;
forming dielectric spacers on sidewalls of the feature; forming metal silicide contacts on the substrate adjacent to the dielectric spacers, wherein portions of the metal silicide contacts are covered by the spacers; and
pulling back the dielectric spacers, wherein outer walls of the dielectric spacers are aligned with edges of the metal silicide contacts, wherein aligning the edges of the dielectric spacers and metal silicide contacts reduces formation of metal pipes.
13. The method of claim 12 comprises pulling back the dielectric spacers to align the outer walls of the dielectric spacers with the edges of the metal silicide contacts.
14. The method of claim 13 wherein pulling back the dielectric spacers comprises an anisotropic etch.
15. The method of claim 13 wherein forming the metal silicide contacts comprises performing first and second annealing processes and pulling back the dielectric spacers is performed between the first and second annealing processes.
16. The method of claim 15 wherein pulling back the dielectric spacers comprises an anisotropic etch.
17. The method of claim 12 wherein the feature comprises a gate of a transistor.
18. The method of claim 17 comprises pulling back the dielectric spacers to align the outer walls of the dielectric spacers with the edges of the metal silicide contacts.
19. A method of fabricating an integrated circuit comprising:
providing a semiconductor body having STI, gate and spacer structures;
forming a Ni or NiPt layer over the structures;
forming TiN cap layer over the structures;
forming first phase Ni silicide layer via RIA1 at 300-400° C., wherein portions of the Ni silicide layer are covered by the spacers;
performing wet clean to remove the TiN cap and unreacted Ni;
dry (plasma) etching of the spacer to have spacer pull-back, wherein outer walls of the spacers are aligned with edges of the Ni silicide contacts; and
forming second phase Ni silicide layer via RTA2 at 400-600° C.
20. The method of claim 19 wherein the Ni or NiPt is deposited using physical vapor deposition.
21. The method of claim 19 wherein the dry etching of the spacer to have spacer pull-back reduces stress of SiN on active and STI divot areas.