ESD protection circuit
View Patent ↗A device having a substrate defined with a device region which includes an ESD protection circuit is disclosed. The ESD protection circuit has first and second transistors. A transistor includes a gate having first and second sides, a first diffusion region in the device region adjacent to the first side of the gate, and a second diffusion region in the device region displaced away from the second side of the gate. The first and second diffusion regions include dopants of a first polarity type. The device includes a first device well which encompasses the device region and second device wells which are disposed within the first device well. A well contact is coupled to the second device wells. The well contact surrounds the gates of the transistors and abuts the first diffusion regions of the transistors.
1. A device comprising:
a substrate defined with a device region, the device region comprises an ESD protection circuit having first and second transistors, wherein a transistor includes
a gate having first and second sides,
a first diffusion region in the device region adjacent to the first side of the gate, and
a second diffusion region in the device region displaced away from the second side of the gate, wherein the second diffusion region is a common second diffusion region of the first and second transistors, wherein the first and second diffusion regions comprise first polarity type dopants;
a first well disposed in the substrate and encompasses the device region, the first well comprises first polarity type dopants;
second wells disposed within the first well, wherein the second wells encompass the first diffusion regions of first and second transistors and not the common second diffusion region, wherein the second wells comprise second polarity type dopants; and
a third well disposed completely within the first well, the third well is disposed below and contiguous with the second diffusion region, wherein the third well comprises first polarity type dopants.
2. The device of claim 1 wherein the third well comprises a lower dopant concentration than the second diffusion region.
3. The device of claim 2 wherein the first polarity type comprises n type and the second polarity type comprises p type.
4. The device of claim 1 further comprising a well contact coupled to the second wells, wherein the well contact surrounds the gates of the transistors and abuts the first diffusion regions of the transistors.
5. The device of claim 1 comprising a drift isolation region disposed between the gate and the second diffusion region.
6. The device of claim 5 wherein the gate overlaps a portion of the drift isolation region.
7. The device of claim 5 wherein the drift isolation region is displaced away from the second diffusion region.
8. The device of claim 1 comprising a sidewall spacer disposed adjacent to the second side of the gate.
9. The device of claim 1 wherein the first diffusion region is a source region and the second diffusion is a drain region.
10. The device of claim 1 wherein the third well comprises a width which is the same as a width of the second diffusion region.
11. The device of claim 1 wherein the first and second diffusion regions, the first well and the third well comprise dopants of a first polarity type and the second wells comprise dopants of a second polarity type.
12. The device of claim 8 wherein the first polarity type comprises n type and the second polarity type comprises p type.
13. The device of claim 12 wherein the second well encompasses at least the well contact, first diffusion region and a part of the gate.
14. A device comprising:
a substrate defined with a device region, the device region comprises an ESD protection circuit having first and second transistors, wherein a transistor includes
a gate having first and second sides,
a first diffusion region in the device region adjacent to the first side of the gate, and
a second diffusion region in the device region displaced away from the second side of the gate, the second diffusion region is a common second diffusion region of the first and second transistors, wherein the first and second diffusion regions comprise dopants of a first polarity type;
a first well encompasses the device region, wherein the first well comprises first polarity type dopants;
second wells disposed within the first well, wherein the second wells encompass the first diffusion regions of the first and second transistors and not the common second diffusion region, the second wells comprise second polarity type dopants;
a third well disposed completely within the first well, the third well is disposed below and contiguous with the second diffusion region, the third well comprises first polarity type dopants; and
a well contact coupled to the second wells, wherein the well contact surrounds the gates of the transistors and abuts the first diffusion regions of the transistors.
15. The device of claim 14 wherein the third well comprises a lower dopant concentration than the second diffusion region.
16. The device of claim 15 wherein the first polarity type comprises n type and the second polarity type comprises p type.
17. The device of claim 14 wherein the second well encompasses at least the well contact, first diffusion region and a part of the gate.
18. The device of claim 4 wherein the second well encompasses at least the first diffusion region and a part of the gate.
19. The device of claim 14 further comprising a drift isolation region disposed within the first well, wherein the drift isolation region is between the gate and second diffusion region.
20. The device of claim 14 wherein the first diffusion region is a source region and the second diffusion is a drain region.