Fin selector with gated RRAM
View Patent ↗A method of fabricating a fin selector with a gated RRAM and the resulting device are disclosed. Embodiments include forming a bottom electrode layer and a hardmask on a semiconductor substrate; etching the hardmask, bottom electrode layer, and semiconductor substrate to form a fin-like structure; forming first and second dummy gate stacks on first and second side surfaces of the fin-like structure, respectively; forming spacers on vertical surfaces of the first and second dummy gate stacks; forming an ILD surrounding the spacers; removing the first and second dummy gate stacks, forming first and second cavities on first and second sides of the fin-like structure; forming an RRAM layer on the first and second side surfaces of the fin-like structure in the first and second cavities, respectively; and filling each of the first and second cavities with a top electrode.
1. A method comprising:
forming a bottom electrode layer and a hardmask on a semiconductor substrate;
etching the hardmask, bottom electrode layer, and semiconductor substrate to form a fin-like structure;
forming first and second dummy gate stacks on first and second side surfaces of the fin-like structure, respectively;
forming spacers on vertical surfaces of the first and second dummy gate stacks;
forming an interlayer dielectric (ILD) surrounding the spacers;
removing the first and second dummy gate stacks, forming first and second cavities on first and second sides of the fin-like structure;
forming a resistive random access memory (RRAM) layer on the first and second side surfaces of the fin-like structure in the first and second cavities, respectively; and
filling each of the first and second cavities with a top electrode.
2. The method according to claim 1 , comprising forming the RRAM layer of a transition metal.
3. The method according to claim 1 , comprising forming the bottom electrode to a thickness of 3 to 20 nanometers and of titanium nitride (TiN), tantalum oxide (TaN), tungsten (W), platinum (Pt), or a multilayer with an oxygen vacancies layer.
4. The method according to claim 1 , further comprising:
forming an oxide on the first and second sides of the substrate of the fin-like structure prior to forming the first and second dummy gate stacks; and
forming the RRAM layer on both the first and second sides of the fin-like structure in the cavity and also on a top surface of the oxide.
5. The method according to 1 , comprising:
forming the RRAM layer on both the first and second side surfaces of the fin-like structure and also on a top surface of the hardmask of the fin-like structure; and
forming a top electrode layer over the RRAM layer and the top electrodes in the first and second cavities.
6. The method according to claim 1 , further comprising
forming a spacer on each of the first and second side surfaces of the semiconductor substrate of the fin-like structure prior to forming the RRAM layer; and
forming the RRAM layer on each spacer and on the first and second side surfaces of the hardmask and the bottom electrode layer in the first and second cavities, respectively.
7. The method according to claim 1 , further comprising forming an access gate on each of the first and second sides of the fin-like structure concurrently with forming the first and second dummy gate stacks.
8. The method according to claim 7 , comprising forming the access gates by:
forming a bottom electrode layer and a hardmask on the semiconductor substrate;
forming an oxide layer on the first and second side surfaces of the fin-like structure; and
forming a polysilicon gate electrode on each oxide layer.