Integrated circuit system with bandgap material and method of manufacture thereof
View Patent ↗A method of manufacturing an integrated circuit system includes: providing a substrate having a channel region; forming a gate stack over a portion of the channel region with the gate stack having a floating gate for storing an electrical charge; forming a source recess in the substrate adjacent to the gate stack; and forming a source by layering a first bandgap material in the source recess.
1. A method of manufacture of an integrated circuit system comprising:
providing a substrate having a channel region;
forming a channel bandgap layer over a portion of the channel region;
forming a gate stack over the channel bandgap layer with the gate stack having a floating gate and non-horizontal sides of the gate stack coplanar with non-horizontal sides of the channel bandgap layer, the floating gate for storing an electrical charge; and
forming an asymmetric structure by layering a first bandgap material adjacent to the gate stack and a second bandgap material, different from the first bandgap material, adjacent to the opposite side of the gate stack.
2. The method as claimed in claim 1 wherein forming the asymmetric structure by layering the first bandgap material includes forming a source with silicon-carbon (Si 1-y C y ) as the first bandgap material.
3. The method as claimed in claim 1 wherein forming the asymmetric structure by layering the second bandgap material includes forming a drain with silicon-germanium (Si 1-x Ge x ) as the second bandgap material.
4. The method as claimed in claim 1 further comprising:
forming a select gate oxide layer over a portion of the channel region; and
forming a select gate over the select gate oxide layer.
5. The method as claimed in claim 1 wherein forming the gate stack includes:
forming a gate oxide over at least a portion of the channel region;
forming the floating gate over the gate oxide;
forming an inter-polysilicon dielectric over the floating gate; and
forming a control gate over the inter-polysilicon dielectric.
6. A method of manufacture of an integrated circuit system comprising:
providing a substrate having a channel region;
forming a channel bandgap layer over a portion of the channel region;
forming a gate stack over the channel bandgap layer with the gate stack having a floating gate and non-horizontal sides of the gate stack coplanar with non-horizontal sides of the channel bandgap layer, the floating gate for storing an electrical charge;
etching a source recess in the substrate adjacent to the gate stack;
forming a source by layering a first bandgap material in the source recess;
forming a drain recess in the substrate adjacent to the gate stack and opposite from the source recess; and
forming an asymmetric structure by layering a second bandgap material, different from the first bandgap material, in the drain recess.
7. The method as claimed in claim 6 wherein:
forming the channel bandgap layer includes layering a channel bandgap material between a source region and a drain region of the substrate.
8. The method as claimed in claim 6 further comprising forming a drain by layering silicon-carbon (Si 1-y C y ) as the second bandgap material in the drain recess.
9. The method as claimed in claim 6 wherein forming the source includes layering silicon-germanium (Si 1-x Ge x ) as the first bandgap material.
10. The method as claimed in claim 6 further comprising forming a drain by layering silicon (Si) as the second bandgap material in the drain recess.
11. An integrated circuit system comprising:
a substrate having a channel region;
a channel bandgap layer over a portion of the channel region;
a gate stack over the channel bandgap layer with the gate stack having a floating gate and non-horizontal sides of the gate stack coplanar with non-horizontal sides of the channel bandgap layer, the floating gate for storing an electrical charge; and
an asymmetric structure including a first bandgap material adjacent to the gate stack and a second bandgap material, different from the first bandgap material, adjacent to the opposite side of the gate stack.
12. The system as claimed in claim 11 further comprising a source formed of the first bandgap material includes silicon-carbon (Si 1-y C y ).
13. The system as claimed in claim 11 further comprising a source formed of the first bandgap material includes silicon-germanium (Si 1-x Ge x ).
14. The system as claimed in claim 11 further comprising:
a select gate oxide layer over a portion of the channel region; and
a select gate over the select gate oxide layer.
15. The system as claimed in claim 11 wherein the gate stack includes:
a gate oxide over at least a portion of the channel region;
the floating gate over the gate oxide;
an inter-polysilicon dielectric over the floating gate; and
a control gate over the inter-polysilicon dielectric.
16. The system as claimed in claim 11 further comprising:
a source; and
a drain adjacent to the channel region and opposite the source, the drain layered with the second bandgap material.
17. The system as claimed in claim 16 further comprising:
a channel bandgap layer grown between a source region of the substrate and a drain region of the substrate, the channel bandgap layer over the substrate.
18. The system as claimed in claim 16 wherein the drain includes silicon-carbon (Si 1-y C y ).
19. The system as claimed in claim 16 wherein the drain includes silicon-germanium (Si 1-x Ge x ).
20. The system as claimed in claim 16 wherein the drain includes silicon (Si).