Step-like spacer profile
View Patent ↗Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a step-like or tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode, etching the spacer material to form a first spacer on each side of the gate electrode, and pulling back the first spacers to form second spacers which have a step-like profile. Embodiments further include depositing a second spacer material over the gate electrode and the second spacers, and etching the second spacer material to form a third spacer on each second spacer, the second and third spacers forming an outwardly tapered composite spacer.
1. A method comprising:
forming a gate electrode on a substrate;
depositing a low temperature oxide (LTO) spacer material over the gate electrode;
etching the LTO spacer material to form a first spacer on each side of the gate electrode; and
pulling back the first spacers to form second spacers.
2. The method according to claim 1 , further comprising:
depositing a second spacer material over the gate electrode and the second spacers; and
etching the second spacer material to form a third spacer on each second spacer, the second and third spacers forming an outwardly tapered composite spacer.
3. The method according to claim 2 , comprising depositing low temperature LTO for the second spacer material.
4. The method according to claim 3 , comprising pulling back the first spacers by wet cleaning.
5. The method according to claim 4 , comprising wet cleaning by applying a dilute hydrogen fluoride (dHF).
6. The method according to claim 5 , comprising etching the second spacer material by reactive ion etching (RIE).
7. The method according to claim 6 , further comprising:
a second wet cleaning;
depositing a third spacer material over the gate electrodes, second spacers, and third spacers; and
etching the third spacer material to form a fourth spacer on each third spacer, the second, third, and fourth spacers forming an outwardly tapered composite spacer.
8. The method according to claim 1 , further comprising:
depositing a resist on the gate electrode and first spacers; and
etching away a portion of the resist prior to pulling back the first spacers.
9. The method according to claim 8 , comprising pulling back the first spacers by wet etching and stripping the resist.
10. The method according to claim 9 , wherein the resist comprises a spin-on resist.
11. The method according to claim 8 , comprising pulling back the first spacers to a height of 40 nm to 120 nm and having a vertical portion having a height of 30 nm to 110 nm.
12. A device comprising:
a substrate;
a gate electrode on the substrate; and
a spacer comprising a low temperature oxide (LTO) on each side of the gate electrode,
wherein each spacer has a tapered or step-like profile.
13. The device according to claim 12 , wherein each spacer has a height less than a height of the gate electrode.
14. The device according to claim 12 , wherein each spacer comprises:
a first spacer having a height less than a height of the gate electrode; and
a second spacer, on the first spacer.
15. The device according to claim 14 , wherein the second spacers each comprise a LTO.
16. The device according to claim 15 , wherein the first and second spacers each have a width of 50 Å to 250 Å.
17. The device according to claim 12 , wherein each spacer comprises a composite spacer of three to five spacers, the spacer closest to the gate electrode having a height less than a height of the gate electrode, and the composite spacer having substantially no vertical portion.
18. A method comprising:
forming at least two gate electrodes on a substrate;
depositing a low temperature oxide (LTO) over the gate electrodes;
etching the LTO to form a first spacer on each side of each gate electrode;
pulling back the first spacers to form second spacers, wherein a profile of the second spacers is more angled than a profile of the first spacers; and
depositing an interlayer dielectric (ILD) on and between the at least two gate electrodes.
19. The method according to claim 18 , comprising pulling back the first spacers by:
depositing a spin-on resist on the gate electrodes and first spacers;
etching away a portion of the spin-on resist;
wet etching; and
stripping the spin-on resist.
20. The method according to claim 18 , wherein the first spacers are pulled back by wet cleaning by applying a dilute hydrogen fluoride (dHF), the method further comprising:
depositing a second LTO over the gate electrode and the second spacers; and
reactive ion etching (RIE) the second LTO to form a third spacer on each second spacer, the second and third spacers forming an outwardly tapered composite spacer.