High density multi-time programmable resistive memory devices and method of forming thereof
Multi-time programmable (MTP) random access memory (RRAM) devices and methods for forming a MTP RRAM device are disclosed. The method includes providing a substrate. The substrate is prepared with at least a first region for accommodating one or more multi-programmable based resistive random access memory (RRAM) cell. A fin-type based selector is provided over the substrate in the first region. A storage element of the RRAM cell is formed over the fin-type based selector. The fin-type based selector is coupled in series with the storage element of the RRAM cell.
1. A semiconductor device comprising:
a substrate including a memory region and a non-memory region;
a first fin structure disposed in the memory region;
a second fin structure disposed in the non-memory region;
a fin-type transistor disposed in the non-memory region, wherein the fin-type transistor comprises a gate disposed on the second fin structure;
a first semiconductor layer disposed over the first fin structure, wherein the first semiconductor layer contacts a top surface and sides of the first fin structure, and the first semiconductor layer comprises first polarity type dopants;
a second semiconductor layer disposed over the first fin structure in the memory region, wherein the second semiconductor layer is disposed over and contacts a top surface of the first semiconductor layer, and the second semiconductor layer comprises second polarity type dopants; and
a storage element disposed over the first fin structure in the memory region, wherein the storage element is disposed above a top surface of the second semiconductor layer, and the storage element is in electrical communication with the second semiconductor layer,
wherein the first semiconductor layer extends over the second fin structure to define elevated source/drain (S/D) regions of the fin-type transistor in the non-memory region.
2. The semiconductor device of claim 1 wherein the storage element comprises a programmable resistive layer and a top electrode disposed over the programmable resistive layer, the programmable resistive layer comprises a high-k dielectric layer, and the top electrode comprises a metal.
3. The semiconductor device of claim 2 wherein the storage element further comprises a bottom electrode disposed between the programmable resistive layer and the second semiconductor layer, and the bottom electrode contacts the top surface of the second semiconductor layer.
4. The semiconductor device of claim 3 wherein the programmable resistive layer covers a top surface of the bottom electrode.
5. The semiconductor device of claim 1 wherein the first fin structure in the memory region comprises the second polarity type dopants.
6. The semiconductor device of claim 1 wherein the first polarity type dopants are p-type dopants, and the second polarity type dopants are n-type dopants.
7. The semiconductor device of claim 2 wherein the programmable resistive layer wraps around a bottom surface and sides of the top electrode.
8. The semiconductor device of claim 1 wherein the storage element comprises a programmable resistive layer and a top electrode disposed over the programmable resistive layer, and the programmable resistive layer wraps around a bottom surface and sides of the top electrode.
9. The semiconductor device of claim 1 wherein the first semiconductor layer includes sides, and the second semiconductor layer wraps around the top surface and the sides of the first semiconductor layer.