Integration of memory, high voltage and logic devices

1. A device comprising:

a substrate having first, second and third regions, the first region includes a memory cell region, the second region includes a peripheral circuit region and the third region includes a logic region;

a memory cell disposed in the first region, wherein

the memory cell comprises a memory transistor which includes a floating gate transistor having a first stack height (T SM ), the floating gate transistor includes a first gate electrode over a first gate dielectric layer on the substrate, a second electrode over the first gate electrode with an isolation layer in between the first and second gate electrodes, and

the T SM is defined by a total thickness of the first gate electrode, isolation layer and the final thickness of the second gate electrode;

a high voltage (HV) transistor disposed in the second region, wherein

the HV transistor having a second stack height (T SHV ), the HV transistor includes a single layer HV gate electrode over and contacts a HV gate dielectric on the substrate, and

the T SHV is defined by a thickness of the single layer HV gate electrode;

a logic transistor disposed in the third region, wherein

the logic transistor having a third stack height (T SL ), the logic transistor includes a single layer logic gate electrode over and contacts a logic gate dielectric on the substrate, and

the T SL is defined by a thickness of the single layer logic gate electrode; and

an interlevel dielectric (ILD) layer disposed over the substrate, wherein the ILD contacts top surfaces of the second gate electrode of the floating gate transistor, the single layer HV gate electrode and the single layer logic gate electrode, and

wherein the first, second and third stack heights are substantially the same across the substrate.

2. The device of claim 1 wherein the second gate electrode includes a heavily doped polysilicon layer.

3. The device of claim 1 wherein the HV transistor includes first spacer elements adjacent to sidewalls of the HV gate electrode, the first spacer elements are substantially wide to achieve a desired HV breakdown voltage.

4. The device of claim 1 wherein stack height variance between the memory, HV and logic transistors is less than or about 10%.

5. A method of forming a device comprising:

providing a substrate having first, second and third regions, the first region includes a memory cell region, the second region includes a peripheral circuit region and the third region includes a logic region;

forming a memory cell in the first region, wherein the memory cell includes a memory transistor having a first stack height (T SM );

forming a high voltage (HV) transistor in the second region, wherein the HV transistor has a second stack height (T SHV ); and

forming a logic transistor in the third region, the logic transistor has a third stack height (T SL ), wherein

the first, second and third stack heights are substantially the same across the substrate, and

forming the memory cell HV transistor and logic transistor comprises

providing a protection stack having first and second protection layers over the third region of the substrate,

forming a first gate dielectric layer over the substrate, wherein the first gate dielectric layer is selectively-grown on the first and second regions of the substrate, and

forming a first gate electrode layer over the first date dielectric layer and the protection stack.

6. The method of claim 5 wherein the first protection layer includes silicon oxide formed on the substrate and the second protection layer includes silicon nitride formed over the silicon oxide.

7. The method of claim 5 wherein forming the memory cell, HV transistor and logic transistor further comprises:

forming an isolation layer over the first gate electrode layer;

forming a second gate electrode layer over the isolation layer; and

patterning the first and second gate electrode layers and the isolation layer to form an interim gate structure over the first region of the substrate.

8. The method of claim 7 wherein forming the memory cell, HV transistor and logic transistor comprises:

removing the second protection layer of the protection stack; and

forming a second gate dielectric layer having varying thicknesses over the first, second and third regions of the substrate, wherein the second gate dielectric layer is formed by a high temperature wet oxidation technique.

9. The method of claim 8 wherein the thickness of the second gate dielectric layer over the second gate layer on the first region is the thickest and the thickness of the second gate dielectric layer over the third region is the thinnest relative to the other regions.

10. The method of claim 8 wherein forming the memory cell, HV transistor and logic transistor comprises:

removing the first protection layer of the protection stack and the second gate dielectric layer on the third region of the substrate; and

forming a third gate dielectric layer over the third region of the substrate.

11. The method of claim 10 wherein forming the memory cell, HV transistor and logic transistor comprises:

forming a third gate electrode layer over the second and third gate dielectric layers; and

forming a dummy processing layer over the third gate electrode layer.

12. The method of claim 11 wherein the dummy processing layer includes silicon nitride.

13. The method of claim 11 wherein forming the memory cell, HV transistor and logic transistor comprises:

patterning the dummy processing and the third gate electrode layers over the second region of the substrate to form gate stack of the HV transistor, wherein the patterned dummy processing layer elevates the height of the HV gate stack for high energy implant for forming extension regions in the second region of the substrate.

14. The method of claim 13 wherein forming the memory cell, HV transistor and logic transistor comprises:

forming first spacer elements on sidewalls of the gate stack of the HV transistor, wherein the first spacer elements are substantially wide to achieve a desired HV breakdown voltage.

15. The method of claim 13 wherein forming the memory cell, HV transistor and logic transistor comprises patterning portions of the first and second gate electrode, first and second gate dielectric and the isolation layers on the first region to form gate stack of the memory transistor prior to forming the first spacer elements.

16. The method of claim 15 wherein the first spacer elements are also formed on sidewalls of the gate stack of the memory transistor.

17. The method of claim 16 wherein forming the memory cell, HV transistor and logic transistor comprises:

removing the dummy processing layers on top of the third gate electrode layers of the MV gate stack and on the third region; and

patterning portions of the third gate layer on the third region to form gate stack of the logic transistor.

18. The method of claim 17 wherein forming the memory cell, HV transistor and logic transistor comprises forming second spacer elements over the first spacer elements on sidewalls of the memory and HV gate stacks, wherein the first and second spacer elements comprise different material.

19. The method of claim 18 wherein the second spacer elements are also formed on and directly contact sidewalls of the gate stack of the logic transistor.

20. A method of forming a device comprising:

providing a substrate having first, second and third regions, the first region includes a memory cell region, the second region includes a peripheral circuit region and the third region includes a logic region;

forming a memory cell in the first region, wherein

the memory cell comprises a memory transistor which includes a floating gate transistor having a first stack height (T SM ), the floating gate transistor includes a first gate electrode over a first gate dielectric layer on the substrate, a second gate electrode over the first gate electrode with an isolation layer in between the first and second gate electrodes, and

the T SM is defined by a total thickness of the first gate electrode, isolation layer and the final thickness of the second gate electrode;

forming a high voltage (HV) transistor in the second region, wherein

the HV transistor has a second stack height (T SHV ), the HV transistor includes a single layer HV gate electrode over and contacts a HV gate dielectric on the substrate, and

the T SHV is defined by a thickness of the single layer HV gate electrode;

forming a logic transistor in the third region, wherein

the logic transistor has a third stack height (T SL ), the logic transistor includes a single layer logic gate electrode over and contacts a logic gate dielectric on the substrate, and

the T SL is defined by a thickness of the single layer logic gate electrode; and

forming an interlevel dielectric (ILD) layer over the substrate, wherein the ILD contacts top surfaces of the second gate electrode of the floating gate transistor, the single layer HV-gate electrode and the single layer logic gate electrode, and

wherein the first, second and third stack heights are substantially the same across the substrate.