Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS
View Patent ↗An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have a silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.
1. A device comprising:
a substrate with first and second active regions;
a first transistor of a first type disposed in the first active region, wherein the first transistor comprises exposed gate sidewalls;
a second transistor of a second-type disposed in the second active region, wherein the second transistor comprises sidewall spacers; and
a stress layer comprising a first stress disposed over both the first and second active regions over the first and second transistors, wherein the first stress of the stress layer affects the second transistor less than the first transistor due to the exposed gate sidewalls of the first transistor.
2. The device of claim 1 wherein:
the first transistor comprises a first gate with the exposed sidewalls and first diffusion regions adjacent to the first gate; and
the second transistor comprises a second gate with sidewall spacers and second diffusion regions adjacent to the second gate.
3. The device of claim 1 comprises a liner lining the second region between the stress layer and the second transistor and the first diffusion regions.
4. The device of claim 1 wherein:
the first stress comprises a tensile stress, the first-type comprises n-type and the second type comprises p-type; or
the first stress comprises a compressive stress, the first-type comprises p-type and the second type comprises n-type.
5. A device comprising:
a substrate prepared with first and second active regions;
a first transistor of a first-type disposed in the first active region, wherein the first transistor comprises exposed gate sidewalls;
a second transistor of a second-type disposed in the second active region, wherein the second transistor comprises sidewall spacers; and
a stress layer comprising a first stress disposed over both the first and second active regions over the first and second transistors, wherein the first stress of the stress layer affects the first transistor more than the second transistor due to the exposed gate sidewalls of the first transistor.
6. The device of claim 5 wherein:
the first stress comprises a tensile stress, the first-type comprises n-type and the second type comprises p-type; or
the first stress comprises a compressive stress, the first-type comprises p-type and the second type comprises n-type.
7. The device of claim 5 wherein:
the first transistor comprises a first gate, first source/drain diffusion regions adjacent to the first gate and a first channel below the first gate between the first source/drain diffusion regions; and
the second transistor comprises a second gate, second source/drain diffusion regions adjacent to the second gate and a second channel below the second gate between the second source/drain diffusion regions.
8. The device of claim 7 wherein:
the first stress comprises a tensile stress, the first-type comprises n-type and the second type comprises p-type; or
the first stress comprises a compressive stress, the first-type comprises p-type and the second type comprises n-type.
9. The device of claim 7 wherein the second gate comprises sidewall spacers, the sidewall spacers cause the first stress of the stress layer to affect the second transistor less than the first transistor.
10. The device of claim 9 comprises a liner lining the second region between the stress layer and the second transistor and the first source/drain diffusion regions.
11. The device of claim 5 comprises a liner lining the second region between the stress layer and the second transistor and first source/drain diffusion regions of the first transistor.
12. A device comprising:
a substrate with first and second active regions;
first and second transistors disposed in the first and second active regions, wherein the first transistor comprises a first-type with exposed gate sidewalls and the second transistor comprises a second type with sidewall spacers; and
a stress layer comprising a stress disposed over both the first and second active regions over the first and second transistors, wherein the stress of the stress layer affects the second transistor less than the first transistor due to the exposed gate sidewalls of the first transistor.
13. The device of claim 12 wherein:
the stress comprises a tensile stress, the first-type comprises n-type and the second type comprises p-type; or
the stress comprises a compressive stress, the first-type comprises p-type and the second type comprises n-type.
14. The device of claim 13 wherein:
the first transistor comprises a first gate with the exposed gate sidewalls, first source/drain diffusion regions adjacent to the first gate and a first channel below the first gate between the first source/drain diffusion regions; and
the second transistor comprises a second gate, second source/drain diffusion regions adjacent to the second gate and a second channel below the second gate between the second source/drain diffusion regions.
15. The device of claim 14 wherein:
the stress comprises a tensile stress, the first-type comprises n-type and the second type comprises p-type; or
the stress comprises a compressive stress, the first-type comprises p-type and the second type comprises n-type.
16. The device of claim 14 wherein the first gate comprises exposed sidewalls and the second gate comprises sidewall spacers, the sidewall spacers cause the stress of the stress layer to affect the second transistor less than the first transistor.
17. The device of claim 16 comprises a liner lining the second region between the stress layer and the second transistor and the first source/drain diffusion regions.
18. The device of claim 12 comprises a liner lining the second region between the stress layer and the second transistor and first source/drain diffusion regions of the first transistor.
19. The device of claim 5 comprises an isolation region separating the active regions.
20. The device of claim 12 comprises an isolation region separating the active regions.