Non-volatile memory device with TSI/TSV application

1. A device comprising:

a semiconductor substrate having an array surface and a non-array surface;

a memory dielectric layer disposed on and contacts the array surface of the substrate;

a memory array having a plurality of memory cells interconnected by first conductors in a first direction and second conductors in a second direction, the memory array is disposed in the memory dielectric layer which is disposed on and contacts the array surface of the substrate;

through silicon via (TSV) contacts disposed in the substrate, the TSV contacts extend from the array surface to the non-array surface, the TSV contacts enable electrical connections to the array surface from the non-array surface; and

a dielectric layer disposed on and contacts the non-array surface of the substrate.

2. The device of claim 1 wherein:

the substrate serves as an interposer substrate; and comprising

interposer contacts which are separated by the dielectric layer from the non-array surface, the interposer contacts to enable electrical connection between the memory array by the TSV contacts; and

interposer pads disposed on the memory dielectric layer to electrically connect the memory array and other circuitry via TSV.

3. The device of claim 2 comprising at least one active component disposed on the memory dielectric layer, wherein the active component comprises a controller device that is connected to the interposer pads.

4. The device of claim 1 wherein the non-array surface of the substrate serves as an active surface of the substrate and the array surface of the substrate serves as an inactive surface of the substrate.

5. The device of claim 4 comprising active components for controlling access to the memory array, wherein the active components are disposed on the non-array surface of the substrate and the dielectric layer covers the active components.

6. The device of claim 1 comprising:

array contacts disposed on a surface of the memory dielectric layer disposed on the array surface, the array contacts are coupled to the TSV contacts to facilitate stacking of the device with another device; and

redistribution layer (RDL) disposed in the memory dielectric layer.

7. The device of claim 1 wherein the memory array is an NVM array.

8. The device of claim 7 wherein the NVM array is a resistive-type NVM array.

9. The device of claim 8 wherein the array is a PCRAM array or a MRAM array.

10. The device of claim 1 wherein a memory cell includes a storage plug disposed between first and second conductors.

11. A method for forming a device comprising:

providing a semiconductor substrate having an array surface and a non-array surface;

forming a dielectric layer on and contacts the non-array surface and forming a memory dielectric layer on and contacts the array surface;

forming TSV contacts extending from the array surface to the non-array surface of the substrate; and

forming a memory array having a plurality of memory cells interconnected by first and second conductors in the memory dielectric layer which is formed on and contacts the array surface, wherein the memory array is coupled to the TSV contacts.

12. The method of claim 11 comprising:

forming the TSV contacts prior to forming the memory array; and

forming interposer pads on the memory dielectric layer to electrically connect the memory array and other circuitry via the TSV contacts.

13. The method of claim 12 comprising forming interposer contacts on the non-array surface of the substrate, the interposer contacts are coupled to the TSV contacts.

14. The method of claim 13 wherein the interposer contacts are separated from the non-array surface of the substrate by the dielectric layer which is formed on and contacts the non-array surface.

15. The method of claim 14 comprising:

processing the memory array side of the substrate first; and

processing the non-memory-array side of the substrate after completing processing of the array side.

16. The method of claim 15 wherein processing the non-memory-array side comprises:

thinning the back side of the substrate to expose the TSV contacts;

forming package contacts coupled to the TSV contacts.

17. The method of claim 11 comprising:

forming at least one active component on the non-array surface of the substrate using FEOL processing, wherein the at least one active component comprises control circuitry

forming the TSV contacts after forming the control circuitry; and

interconnecting the TSV contacts to the control circuitry using BEOL processing, wherein the dielectric layer covers the at least one active component.

18. The method of claim 17 comprises:

processing the array surface of the substrate after processing the non-array surface of the substrate;

thinning the array surface to expose the TSV contacts; and

forming a redistribution layer (RDL) in the memory dielectric layer which is formed on and contacts the array surface, wherein the RDL and memory array are formed together in the memory dielectric layer and the memory array is interconnected to the TSV contacts.

19. The method of claim 18 wherein the memory array comprises a resistive-type NVM array.

20. A method for forming a NVM memory device comprising:

providing a semiconductor substrate having an array surface and a non-array surface;

forming a memory dielectric layer on and contacts the array surface and forming a dielectric layer on and contacts the non-array surface;

forming TSV contacts extending from the array surface to the non-array surface of the substrate;

forming at least one active component on the non-array surface, wherein the dielectric layer covers the at least one active component; and

forming a resistive type NVM having a plurality of memory cells interconnected by first and second conductors in the memory dielectric layer which is formed on and contacts the array surface of the substrate, wherein the resistive type NVM is coupled to the TSV contacts.