High sensing margin magnetic resistive memory device in which a memory cell read and write select transistors to provide different read and write paths

1. A memory device with high sensing margin comprising:

a memory cell having a storage unit coupled to a cell selector unit, wherein

the storage unit comprises first and second storage elements, wherein each of the first and second storage elements comprises first and second terminals, wherein the second terminal of the first storage element is coupled to a write source line (SL-W) and the second terminal of the second storage element is coupled to a bit line (BL), and

the cell selector unit comprises first and second selectors, wherein the first selector comprises a write select transistor (T W ) and the second selector comprises a first read transistor (T R1 ) and a second read transistor (T R2 ), wherein

the dimensions of both T R1 and T R2 are smaller than the T W ,

the first selector is coupled to a word line (WL) for selectively coupling a write path to the storage unit, and

the second selector is coupled to a read line (RL) for selectively coupling a read path to the storage unit.

2. The memory device of claim 1 wherein the memory cell is a spin torque transfer-magnetic random access memory (STT-MRAM).

3. The memory device of claim 1 wherein the first storage element comprises a first magnetic tunnel junction (MTJ 1 ) element and the second storage element comprises a second magnetic tunnel junction (MTJ 2 ) element.

4. The memory device of claim 3 wherein:

the T W comprises a gate terminal, a first source terminal (S TW ) and a second drain terminal (D TW );

the T R1 comprises a gate terminal, a first source terminal (S TR1 ) and a second drain terminal (D TR1 ); and

the T R2 comprises a gate terminal, a first source terminal (S TR2 ) and a second drain terminal (D TR2 ).

5. The memory device of claim 4 wherein the S TW of T W is coupled to the first terminal of the MTJ 1 and the D TW of T W is coupled to the first terminal of the MTJ 2 and the gate terminal of T W is coupled to the WL.

6. The memory device of claim 5 wherein:

the first source terminals S TR1 and S TR2 of T R1 and T R2 are coupled to a read source line (SL-R);

the second drain terminal D TR1 of T R1 is commonly coupled to the first terminal of the MTJ 1 and S TW while the second drain terminal D TR2 of T R2 is commonly coupled to the first terminal of the MTJ 2 and the D TW ; and

the gate terminals of T R1 and T R2 are coupled to the RL.

7. The memory device of claim 6 wherein the SL-W and the BL are coupled to a sense amplifier.

8. The memory device of claim 1 comprising a substrate prepared with a memory cell region having a write transistor active region and first and second read transistor active regions, wherein the T W is disposed in the write transistor active region, the T R1 is disposed in the first read transistor active region and the T R2 is disposed in the second read transistor active region.

9. The memory device of claim 8 wherein the T R1 and T R2 are aligned adjacent in a row direction and the T W is aligned adjacent to the T R1 and T R2 in a column direction within the memory cell region.

10. The memory device of claim 9 wherein:

the T W comprises a gate, a first source region (S TW ) and a second drain region (D TW ), wherein the gate of T W serves as the WL and traverses the write transistor active region;

the T R1 comprises a gate, a first source region (S TR1 ) and a second drain region (D TR1 ); and

the T R2 comprises a gate, a first source region (S TR2 ) and a second drain region (D TR2 ), wherein the gate of T R1 and the gate of T R2 are a common gate which serves as the RL and traverses the first and second read transistor active regions.

11. The memory device of claim 10 comprising a dielectric layer having at least a first ILD level and a second ILD level disposed over the substrate, wherein the first ILD level comprises a pre-metal dielectric level and a first metal level (M1) while the second ILD level comprises a via level (V1) and a second metal level (M2).

12. The memory device of claim 11 wherein a read source line (SL-R) is disposed in M1 and the source regions S TR1 and S TR2 of the T R1 and T R2 are commonly coupled to the SL-R through contacts disposed in V1.

13. The memory device of claim 12 wherein the first and second storage elements are disposed in a storage dielectric layer over the M1, the first storage element is coupled to the first source region S TW of T W and second drain region D TR1 of T R1 , while the second storage element is coupled to the second drain region D TW of T W and the second drain region D TR2 of T R2 .

14. The memory device of claim 13 wherein the SL-W and BL are disposed in M2 and the SL-W is coupled to the first storage element while the BL is coupled to the second storage element.

15. A method of operating a memory device with high sensing margin comprising:

providing a memory cell having a storage unit coupled to a cell selector unit, wherein

the storage unit comprises first and second storage elements, wherein each of the first and second storage elements comprises first and second terminals, wherein the second terminal of the first storage element is coupled to a write source line (SL-W) and the second terminal of the second storage element is coupled to a bit line (BL), and

the cell selector unit comprises first and second selectors, wherein the first selector comprises a write select transistor (T W ) and the second selector comprises a first read transistor (T R1 ) and a second read transistor (T R2 ), wherein

the dimensions of both T R1 and T R2 are smaller than the T W ,

the first selector is coupled to a word line (WL), and

the second selector is coupled to a read line (RL); and

performing a read operation or write operation with the memory cell, wherein

when a write operation is performed, the T R1 and T R2 are switched off while the T W is switched on for selectively coupling a write path to the storage unit, and

when a read operation is performed, the T W is switched off while the T R1 and T R2 are switched on for selectively coupling a read path to the storage unit.

16. A method for forming a memory device with high sensing margin comprising:

forming a memory cell which comprises forming a storage unit and a cell selector unit, wherein the storage unit is coupled to the cell selector unit, and wherein

forming the storage unit comprises forming first and second storage elements, wherein each of the first and second storage elements comprises first and second terminals, coupling the second terminal of the first storage element to a write source line (SL-W) and coupling the second terminal of the second storage element to a bit line (BL), and

forming the cell selector unit comprises forming first and second selectors, wherein the first selector comprises a write select transistor (T W ) and the second selector comprises a first read transistor (T R1 ) and a second read transistor (T R2 ), wherein the dimensions of both T R1 and T R2 are smaller than the T W , and coupling the first selector to a word line (WL) for selectively coupling a write path to the storage unit and coupling the second selector to a read line (RL) for selectively coupling a read path to the storage unit.

17. The method of claim 16 comprising providing a substrate prepared with a memory cell region having a write transistor active region and first and second read transistor active regions, wherein the T W is formed in the write transistor active region, the T R1 is formed in the first read transistor active region and the T R2 is formed in the second read transistor active region.

18. The method of claim 17 wherein the T R1 and T R2 are aligned adjacent in a row direction and the T W is aligned adjacent to the T R1 and T R2 in a column direction within the memory cell region.

19. The method of 18 wherein forming the T W and the T R1 and T R2 comprises:

forming a gate dielectric layer and a gate electrode layer over the substrate;

patterning the gate dielectric and gate electrode layers to define gates of the T W , T R1 and T R2 ;

performing an implant to form a first source region (S TW ) and a second drain region (D TW ) adjacent to first and second sides of the gate of T W , a first source region (S TR1 ) and a second drain region (D TR1 ) adjacent to first and second sides of the gate of T R1 , and a first source region (S TR2 ) and a second drain region (D TR2 ) adjacent to first and second sides of the gate of T R2 .

20. The method of claim 19 wherein the gate of the T W serves as the WL and the gate of T R1 and the gate of T R2 are a common gate which serves as the RL and traverses the first and second read transistor active regions.