3D MRAM with through silicon vias or through silicon trenches magnetic shielding
Emerging memory chips and methods for forming an emerging memory chip are presented. For example, magnetoresistive random access memory (MRAM) chip magnetic shielding and vertical stacking capabilities processed at the wafer-level are disclosed. The method includes providing a magnetic shield in the through silicon vias and/or through silicon trenches surrounding or adjacent to magnetic tunnel junction (MTJ) array within the MRAM region and also at the front side and back side of the chip. Magnetic shield in the through silicon trenches connects front side and back side magnetic shield. Magnetic shield in the through silicon vias provides vertical stacking, magnetic shielding and electrical connection of the MRAM chips to form 3D IC packages. This magnetic shielding method is applicable for both in-plane and perpendicular MRAM chips. The MTJ array is formed in the MRAM region and in between adjacent inter layer dielectric (ILD) levels of the upper ILD layer in the back end of line (BEOL) of the MRAM chip.
1. A method of forming a magnetoresistive random access memory (MRAM) chip comprising:
providing a substrate having first and second surfaces, wherein the first surface is defined with a MRAM region and the second surface of the substrate defines a back side of the MRAM chip;
forming an upper inter level dielectric (ILD) layer over the first surface of the substrate, wherein the upper ILD layer comprises a plurality of ILD levels; and
forming a magnetic storage element having a magnetic tunneling junction (MTJ) array with MTJ stack in the MRAM region and in between adjacent ILD levels of the upper ILD layer;
forming a pad level over the magnetic storage element, wherein the pad level defines a front side of the MRAM chip; and
forming at least a through silicon via magnetic shield contact structure which extends from the front side to the back side of the MRAM chip.
2. The method of claim 1 comprising forming a pad interconnect in the pad level.
3. The method of claim 2 wherein the pad interconnect couples the through silicon via magnetic shield contact structure to the magnetic storage element.
4. The method of claim 1 wherein forming at least a through silicon via magnetic shield contact structure comprises:
forming a deep via adjacent to the magnetic storage element, wherein the deep via extends from a top surface of the pad level and partially into a portion of the substrate; and
patterning the pad level to define a pad interconnect opening which is in communication with the deep via, wherein the pad interconnect opening comprises a pad opening and a via opening.
5. The method of claim 4 wherein forming at least a through silicon via magnetic shield contact structure further comprises completely and simultaneously filling the deep via and the pad interconnect opening with a magnetic shield layer to form the through silicon via magnetic shield contact structure in the deep via and a pad interconnect in the pad level, wherein the through silicon via magnetic shield contact structure and the pad interconnect form a single unitary contact structure.
6. The method of claim 1 comprising forming a passivation layer covering the pad level and the through silicon via magnetic shield contact structure.
7. The method of claim 6 comprising:
forming a die bump pad opening through a portion of the passivation layer over the front side of the MRAM chip;
forming a die microbump in the die bump pad opening and coupling the die microbump to the through silicon via magnetic shield contact structure; and
performing a removal process on the second surface of the substrate to expose a bottom surface of the through silicon via magnetic shield contact structure.
8. The method of claim 1 comprising forming a through silicon trench magnetic shield structure which extends from the front side to the back side of the MRAM chip and surround the MTJ array.
9. The method of claim 8 comprising:
forming a passivation layer covering the pad level, the through silicon via magnetic shield contact structure and the through silicon trench magnetic shield structure; and
patterning the passivation layer to form an opening which exposes a top surface of the through silicon trench magnetic shield structure.
10. The method of claim 9 comprising:
forming a front side magnetic shield layer over the front side of the MRAM chip, wherein the front side magnetic shield layer is coupled to the top surface of the through silicon trench magnetic shield structure; and
forming a back side magnetic shield layer over the back side of the MRAM chip, wherein the back side magnetic shield layer is coupled to a bottom surface of the through silicon trench magnetic shield structure.
11. The method of claim 1 comprising:
forming deep vias and trenches within the prime die region, wherein the deep vias and trenches comprise first type via opening which accommodates the through silicon via magnetic shield contact structure and second type trench opening which accommodates the through silicon trench magnetic shield structure, wherein the deep vias and trenches extend from a top surface of the pad level and partially into a portion of the substrate; and
patterning the pad level to define a pad interconnect opening which is in communication with the first type via opening of the deep via, wherein the pad interconnect opening comprises a pad opening and a via opening.
12. The method of claim 11 comprising completely and simultaneously filling the deep vias and trenches and the pad interconnect opening with a magnetic shield layer to form the through silicon via magnetic shield contact structure in the first type via opening and a pad interconnect in the pad level as well as the through silicon trench magnetic shield structure in the second type trench opening.
13. A magnetoresistive random access memory (MRAM) chip comprising:
a substrate having first and second surfaces, wherein the first surface is defined with a MRAM region and the second surface of the substrate defines a back side of the MRAM chip;
an upper inter level dielectric (ILD) layer disposed over the first surface of the substrate, wherein the upper ILD layer comprises a plurality of ILD levels; and
a magnetic storage element having a magnetic tunneling junction (MTJ) array with MTJ stack disposed in the MRAM region and in between adjacent ILD levels of the upper ILD layer;
a pad level disposed over the magnetic storage element, wherein the pad level defines a front side of the MRAM chip; and
at least a through silicon via magnetic shield contact structure which extends from the front side to the back side of the MRAM chip.
14. The MRAM chip of claim 13 comprising a pad interconnect disposed in the pad level.
15. The MRAM chip of claim 14 wherein the pad interconnect couples the through silicon via magnetic shield contact structure to the magnetic storage element.
16. The MRAM chip of claim 14 wherein the pad interconnect and the through silicon via magnetic shield contact structure include a magnetic shield material to form a single unitary contact structure.
17. The MRAM chip of claim 16 wherein the magnetic shield material includes NiFe (Mμ metal).
18. The MRAM chip of claim 13 comprising a through silicon trench magnetic shield structure which extends from the front side to the back side of the MRAM chip and surround the MTJ array.
19. The MRAM chip of claim 18 wherein the through silicon via magnetic shield contact structure and the through silicon trench magnetic shield structure comprise the same magnetic shield material.
20. The MRAM chip of claim 18 comprising:
a front side magnetic shield layer disposed over the front side of the MRAM chip, wherein the front side magnetic shield layer is coupled to a top surface of the through silicon trench magnetic shield structure; and
a back side magnetic shield layer disposed over the back side of the MRAM chip, wherein the back side magnetic shield layer is coupled to a bottom surface of the through silicon trench magnetic shield structure.