Integrated circuits having copper bonding structures with silicon carbon nitride passivation layers thereon and methods for fabricating same

1. A integrated circuit comprising:

a substrate;

a copper bond pad having a contact surface, the copper bond pad overlying the substrate;

a passivation layer comprising silicon carbon nitride disposed on the contact surface; and

a conductive element bonded to the copper bond pad through the passivation layer with a weld.

2. The integrated circuit of claim 1 , wherein the passivation layer has a thickness of from about 3 to about 15 nanometers (nm).

3. The integrated circuit of claim 2 , wherein the passivation layer has a thickness of from about 5 to about 8 nm.

4. The integrated circuit of claim 1 , wherein the copper bond pad comprises pure copper, doped copper, or a copper alloy.

5. The integrated circuit of claim 4 , wherein the doped copper comprises at least 90 weight percent (wt %) copper based on a total weight of the bond pad.

6. The integrated circuit of claim 5 , wherein the doped copper comprises aluminum, manganese, gold or a combination thereof.

7. The integrated circuit of claim 4 , wherein the copper alloy comprises at least 55 wt % copper based on a total weight of the copper bond pad.

8. The integrated circuit of claim 7 , wherein the copper alloy comprises aluminum, gold, or a combination thereof.

9. The integrated circuit of claim 1 , wherein the conductive element is bonded to the copper bond pad through the passivation layer with a ball bond forming the weld.

10. The integrated circuit of claim 9 , wherein the conductive element is a wire.

11. The integrated circuit of claim 1 , wherein the passivation layer comprises stoichiometric silicon carbon nitride SiCN.

12. A method for fabricating an integrated circuit comprising the steps of:

providing a semiconductor substrate having a copper bond pad overlying a surface of the semiconductor substrate, the copper bond pad having a contact surface;

forming a passivation layer comprising silicon carbon nitride on the contact surface of the copper bond pad using a chemical vapor deposition (CVD) technique; and

bonding a conductive element to the copper bond pad through the passivation layer with a weld.

13. The method of claim 12 , wherein forming the passivation layer comprises forming the passivation layer by plasma enhanced chemical vapor deposition (PECVD).

14. The method of claim 13 , wherein the PECVD is performed at a temperature in a range of from about 250 to about 400° C.

15. The method of claim 13 , wherein the PECVD is performed using radio frequency (RF) energy in a range of from about 180 to about 500 Watts.

16. The method of claim 13 , wherein the PECVD is performed at a deposition rate of no greater than about 3 nanometers (nm) per 5 seconds (s) (0.6 nm/s).

17. The method of claim 16 , wherein the PECVD is performed at a deposition rate of no greater than about 3 nm per 8 seconds (s) (3 nm/8 s).

18. The method of claim 13 , wherein the PECVD is performed for a period of time required to form the passivation layer having a thickness from about 3 to about 15 nanometers (nm).

19. The method of claim 12 , further comprising electrically coupling the copper bond pad to the conductive element after forming the passivation layer.

20. A method for fabricating an integrated circuit, the method comprising the steps of:

providing a semiconductor substrate having a copper bond pad overlying a surface of the semiconductor substrate, the copper bond pad having a contact surface;

depositing a passivation layer comprising silicon carbon nitride on the contact surface of the copper bond pad using plasma-enhanced chemical vapor deposition; and

electrically coupling a conductive element to the copper bond pad through the passivation layer with a weld after depositing the passivation layer.