RRAM structure with improved memory margin

1. A method comprising:

forming an interlayer dielectric (ILD) over a bottom electrode;

forming a sacrificial layer over the ILD;

removing a portion of the ILD and a portion of the sacrificial layer vertically contiguous with the portion of the ILD, forming a cell area;

forming a metal layer within the cell area;

forming an interlayer dielectric structure above or surrounded by and protruding above the metal layer, a top surface of the interlayer dielectric structure being coplanar with a top surface of the sacrificial layer;

removing the sacrificial layer;

forming a memory layer on the ILD and/or on side surfaces of the interlayer dielectric structure; and

forming a dielectric layer surrounding at least a portion of the interlayer dielectric structure.

2. A method according to claim 1 , comprising:

forming the memory layer prior to forming the sacrificial layer;

forming the dielectric layer on the memory layer after removing the sacrificial layer; and

removing a portion of the memory layer from the ILD not under the dielectric layer.

3. A method according to claim 1 , comprising:

forming the memory layer on side surfaces of the portion of the interlayer dielectric structure above the metal layer; and

forming the dielectric layer surrounding the memory layer.

4. A method according to claim 1 , comprising:

forming the memory layer on side surfaces of the portion of the interlayer dielectric structure and on the ILD; and

forming the dielectric layer above the memory layer on the ILD and surrounding the memory layer on the side surfaces of the portion of the interlayer dielectric structure.

5. A method according to claim 1 , comprising forming the metal layer as rectangular-shaped within the cell area below the interlayer dielectric structure.

6. A method according to claim 5 , comprising forming a top surface of the metal layer above a top surface of the ILD.

7. A method according to claim 1 , comprising forming the metal layer as u-shaped within the cell area and between the memory layer and interlayer dielectric structure with a top surface of the u-shaped metal layer being coplanar with a top surface of the memory layer.

8. A method according to claim 7 , comprising:

forming the memory layer on the ILD; and

forming a top surface of the metal layer coplanar with a top surface of the memory layer.

9. A method according to claim 1 , further comprising forming a top electrode over the ILD, the dielectric layer, and the interlayer dielectric structure.

10. A method comprising:

forming an interlayer dielectric (ILD) over a bottom electrode;

forming a sacrificial layer on the ILD;

removing a portion of the ILD and the sacrificial layer, forming a cavity;

forming a metal layer within the cavity;

filling the cavity with an interlayer dielectric material;

removing the sacrificial layer exposing at least a portion of the interlayer dielectric material;

forming a memory layer on side surfaces of the interlayer dielectric material and/or on the ILD surrounding the interlayer dielectric material;

forming a dielectric layer surrounding the interlayer dielectric material and/or the memory layer; and

forming a top electrode over the ILD, the dielectric layer, and the interlayer dielectric material.