Grain boundary blocking for stress migration and electromigration improvement in CU interconnects
View Patent ↗Example embodiments of a structure and method for forming a copper interconnect having a doped region near a top surface. The doped region has implanted alloying elements that block grain boundaries and reduce stress and electro migration. In a first example embodiment, the barrier layer is left over the inter metal dielectric layer during the alloying element implant. The barrier layer is later removed with a planarization process. In a second example embodiment the barrier layer is removed before the alloying element implant and a hard mask blocks the alloying element from being implanted in the inter metal dielectric layer.
1. A method to fabricate an interconnect structure comprising:
providing a substrate prepared with an intermetal dielectric having an interconnect with an interconnect top surface which is coplanar with an intermetal dielectric top surface of the intermetal dielectric;
forming a top doped region comprising non-metallic dopants, wherein forming the top doped region comprises
providing the non-metallic dopants having a first dopant concentration in a top portion of the interconnect, and
annealing the substrate, wherein annealing causes the non-metallic dopants in the top portion of the interconnect to block at least some grain boundaries in the top doped region, wherein a lower portion of the interconnect below the top doped region is substantially free of the non-metallic dopants as compared to the top doped region.
2. The method of claim 1 wherein:
the interconnect comprises copper; and
the doped region spans across the entire interconnect top surface.
3. The method of claim 1 wherein:
the interconnect comprises copper; and
the doped region covers the entire interconnect top surface, the first dopant concentration comprises less than about 1 atomic %.
4. The method of claim 1 wherein:
the interconnect comprises copper; and
the non-metallic dopants are selected from N, B, P, Si and C or combinations thereof; and
the first dopant concentration comprises less than about 1 atomic %.
5. The method of claim 1 wherein the interconnect is formed in a dual damascene opening in the intermetal dielectric, the dual damascene opening comprising a top line opening and a bottom via plug opening.
6. The method of claim 1 wherein:
the interconnect comprises copper; and
the first dopant concentration comprises about 0.1 atomic % to 1.0 atomic %.
7. The method of claim 1 wherein:
the interconnect comprises copper;
the interconnect is formed in a dual damascene opening in the intermetal dielectric, the dual damascene opening comprising a top line opening for an interconnect line and a bottom via plug opening for an interconnect plug; and
the doped region has a depth of about 7 to 12% a height of the interconnect line.
8. The method of claim 1 wherein the doped region extends across the entire interconnect top surface.
9. The method of claim 1 wherein the doped region has a final depth between about 100 and 1000 Å.
10. A method of forming a device comprising:
providing a substrate prepared with an intermetal dielectric with an interconnect, wherein an interconnect top surface of the interconnect is coplanar with the intermetal dielectric top surface of the intermetal dielectric; and
forming a top doped region at a top portion of the interconnect, the top doped region comprises non-metallic dopants having a first dopant concentration, the non-metallic dopants block at least some grain boundaries in the top doped region, wherein a lower portion of the interconnect below the top doped region is substantially free of non-metallic dopants as compared with the top doped region.
11. The method of claim 10 wherein an interconnect barrier layer lines the intermetal dielectric top surface and interconnect, wherein the interconnect top surface of the interconnect is coplanar with a barrier top surface of the barrier layer.
12. The method of claim 11 wherein portions of the barrier layer lining the intermetal dielectric top surface are removed after forming the doped region.
13. The method of claim 11 wherein portions of the barrier layer lining the intermetal dielectric top surface are removed prior to forming the doped region.
14. The method of claim 10 wherein:
a hard mask is provided on the intermetal dielectric top surface, the hard mask is used to pattern a trench in the intermetal dielectric for the interconnect; and
an interconnect barrier layer lining the trench and a hard mask top surface of the hard mask, wherein the interconnect top surface is coplanar with a barrier top surface of the barrier layer.
15. The method of claim 14 wherein portions of the barrier layer lining the hard mask top surface of the hard mask are removed after forming the doped region.
16. The method of claim 14 wherein portions of the barrier layer lining the hard mask top surface of the hard mask are removed prior to forming the doped region.
17. The method of claim 10 further comprises an anneal to diffuse the dopants of the doped region to block the grain boundaries.
18. The method of claim 10 wherein the non-metallic dopants comprise B, P, N, Si, C or a combination thereof.
19. The method of claim 10 wherein the first dopant concentration comprises about 0.1-1.0 atomic percent.
20. The method of claim 10 wherein the interconnect comprises copper.
21. A method of forming an interconnect comprising:
providing a substrate prepared with an intermetal dielectric having a trench therein corresponding to an interconnect;
forming a conductive layer on the substrate, the conductive layer covering the intermetal dielectric and filling the trench;
planarizing the substrate to remove excess conductive layer to form the interconnect in the trench, wherein an interconnect top surface of the interconnect is coplanar with an interconnect dielectric top surface of the interconnect dielectric; and
forming a top doped region at a top portion of the interconnect, the top doped region comprising non-metallic dopants having a first dopant concentration, the non-metallic dopants block at least some grain boundaries of the interconnect in the top doped region, wherein a lower portion of the interconnect below the top doped region is substantially free of non-metallic dopants as compared with the top doped region.
22. A method of forming an interconnect in a semiconductor device comprising:
providing a substrate prepared with an intermetal dielectric having a trench therein corresponding to an interconnect;
forming a conductive layer on the substrate, the conductive layer covering the intermetal dielectric and filling the trench;
planarizing the substrate to remove excess conductive layer to form the interconnect in the trench, wherein an interconnect top surface of the interconnect is coplanar with an interconnect dielectric top surface of the interconnect dielectric; and
forming a top doped region comprising non-metallic dopants, wherein forming the top doped region comprises
providing the non-metallic dopants having a first dopant concentration in a top portion of the interconnect, and
annealing the substrate, wherein annealing causes the non-metallic dopants in the top portion of the interconnect to block at least some grain boundaries in the top doped region, wherein a lower portion of the interconnect below the top doped region is substantially free of the non-metallic dopants as compared to the top doped region.