LDMOS with improved breakdown voltage
An LDMOS is formed with a field plate over the n − drift region, coplanar with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second coplanar gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack of a high-k metal gate and the second gate stack of a field plate on a gate oxide layer, forming the first and second gate stacks with different gate electrode materials on a common gate oxide, and forming the gate stacks separated from each other and with different gate dielectric materials.
1. A device comprising:
a substrate;
a first well and a second well in the substrate, the first well being doped with a first conductivity type dopant, the second well being doped with a second conductivity type dopant, and the second well surrounding the first well;
a source in the first well and a drain in the second well;
a doped region of the first conductivity type dopant in the first well, the doped region functioning as a body contact to the first well;
first and second coplanar gate stacks on the substrate, the first gate stack being formed on a portion of the first well, and the second gate stack being formed on a portion of the second well, the first gate stack and the second gate stack being adjacent each other with no intervening structure; wherein
the work function of the second gate stack is higher than the work function of the first gate stack.
2. The device according to claim 1 , comprising:
a first oxide layer and a polysilicon or amorphous silicon (a-Si) field plate as the second gate stack; and
a high-k dielectric layer, or a second oxide and a high-k dielectric layer, and a metal gate as the first gate stack.
3. The device according to claim 2 , comprising a p+ doped a-Si field plate on the first oxide layer.
4. The device according to claim 1 , comprising:
an oxide layer on the substrate over the portion of the first well and the portion of the second well;
a first gate material on the oxide layer over the portion of the first well, forming the first gate stack; and
a second gate material, having a higher work function than the first gate material, on the oxide layer over the portion of the second well, forming the second gate stack.
5. The device according to claim 4 , comprising:
an n+ doped amorphous silicon or polysilicon as the first gate material; and
a p+ doped amorphous silicon or polysilicon as the second gate material.
6. The device according to claim 4 , comprising:
antimony (Sb) doped polysilicon as the first gate material; and
undoped polysilicon as the second gate material.
7. The device according to claim 4 , comprising: tantalum nitride (TaN) as the first gate material; and titanium nitride (TiN) as the second gate material.
8. The device according to claim 1 , comprising:
a first dielectric layer, or a first oxide layer and a first dielectric layer, and a metal gate as the first gate stack, the first dielectric layer having a first work function; and
a second dielectric layer, or a second oxide layer and a second dielectric layer, and a metal gate as the second gate stack, the second dielectric layer having a second work function different from the first work function, and the first gate stack being separated from the second gate stack.
9. The device according to claim 8 , comprising:
a dielectric layer implanted with a first dopant as the first dielectric layer; and
the same dielectric layer implanted with a second dopant as the second dielectric layer, the second dopant being different from the first dopant.
10. A device comprising:
a substrate;
a lateral diffused metal-oxide semiconductor (LDMOS) formed on the substrate, the LDMOS comprising:
a first well and a second well in the substrate, the first well being doped with a first conductivity type dopant, the second well being doped with a second conductivity type dopant, and the second well surrounding the first well;
first and second coplanar gate stacks on the substrate, each having a gate dielectric and a gate material on the gate dielectric, the first gate stack being formed on a portion of the first well, and the second gate stack being formed on a portion of the second well; wherein no portion of the second gate stack is formed on a portion of the first well; and
wherein the gate dielectrics and/or the gate materials of the first and second gate stacks are different and
the work function of the second gate stack is higher than the work function of the first gate stack.
11. The device according to claim 10 , comprising:
a first oxide layer and a polysilicon or amorphous silicon (a-Si) field plate as the second gate stack; and
a high-k dielectric layer, or a second oxide and a high-k dielectric layer, and a metal gate as the first gate stack.
12. The device according to claim 11 , comprising a p+ doped a-Si field plate on the first oxide layer.
13. The device according to claim 10 , comprising:
an oxide layer on the substrate over the portion of the first well and the portion of the second well;
a first gate material on the oxide layer over the portion of the first well, forming the first gate stack; and
a second gate material, having a higher work function than the first gate material, on the oxide layer over the portion of the second well, forming the second gate stack.
14. The device according to claim 13 , comprising: an n+ doped amorphous silicon or polysilicon as the first gate material; and
a p doped amorphous silicon or polysilicon as the second gate material.
15. The device according to claim 13 , comprising:
antimony (Sb) doped polysilicon as the first gate material; and undoped polysilicon as the second gate material.
16. The device according to claim 13 , comprising: tantalum nitride (TaN) as the first gate material; and titanium nitride (TiN) as the second gate material.
17. The device according to claim 10 , comprising:
a first dielectric layer, or a first oxide layer and a first dielectric layer, and a metal gate as the first gate stack, the first dielectric layer having a first work function; and
a second dielectric layer, or a second oxide layer and a second dielectric layer, and a metal gate as the second gate stack, the second dielectric layer having a second work function different from the first work function, and the first gate stack being separated from the second gate stack.
18. The device according to claim 17 , comprising:
a dielectric layer implanted with a first dopant as the first dielectric layer; and
the same dielectric layer implanted with a second dopant as the second dielectric layer, the second dopant being different from the first dopant.
19. A device comprising: a substrate;
a first well and a second well in the substrate, the first well being doped with a first conductivity type dopant, the second well being doped with a second conductivity type dopant, and the second well surrounding the first well;
a source in the first well and a drain in the second well;
a doped region of the first conductivity type dopant in the first well, the doped region functioning as a body contact to the first well;
first and second coplanar gate stacks on the substrate, the second gate stack being formed of a first oxide layer and a first gate material of doped polysilicon or amorphous silicon (a-Si) on a portion of the second well, with no portion of the second gate stack being formed on a portion of the first well, and the first gate stack being formed of a dielectric layer and a second gate material different than the first gate material on a portion of the first well; wherein
the work function of the second gate stack is higher than the work function of the first gate stack.
20. The device according to claim 19 , wherein the dielectric layer and second gate material comprise:
a high-k dielectric layer, or a second oxide and a high-k dielectric layer, and a metal gate, or the first oxide layer and a gate material having a lower work function than the first gate material, or
the first oxide layer and an n+ doped amorphous silicon or polysilicon.
21. The device according to claim 1 , wherein no portion of the second gate stack is formed on a portion of the first well.