Efficient optical proximity correction repair flow method and apparatus
View Patent ↗A method and apparatus for an efficient optical proximity correction (OPC) repair flow is disclosed. Embodiments may include receiving an input data stream of an integrated circuit (IC) design layout, performing one or more iterations of an OPC step and a layout polishing step on the input data stream, and performing a smart enhancement step if an output of a last iteration of the OPC step fails to satisfy one or more layout criteria and if a number of the one or more iterations satisfies a threshold value. Additional embodiments may include performing a pattern insertion process cross-linked with the OPC step, the pattern insertion process being a base optical rule check (ORC) process.
1. A computer-implemented method comprising:
receiving, by way of a processor, an input data stream of an integrated circuit (IC) design layout;
correcting, by the processor, identified outliers in the IC design layout by way of an iterative repair loop comprising steps of:
performing one or more iterations of an optical proximity correction (OPC) step and a layout polishing step on the input data stream;
performing, by the processor, a smart enhancement step if an output of a last iteration of the OPC step fails to satisfy one or more layout criteria and if a number of the one or more iterations satisfies a threshold value, the smart enhancement step comprising an inverse lithography technology (ILT) process;
cross-linking, by the processor, a base optical rule check (ORC) process with the OPC step; and
performing, by the processor, pattern classification during the one or more iterations of the OPC step,
wherein the pattern classification is based on a pattern matching database or one or more compensation tables.
2. The method according to claim 1 , further comprising:
performing an additional OPC step after the smart enhancement step; and
performing an additional smart enhancement step if an output of the additional OPC step fails to satisfy the one or more layout criteria.
3. The method according to claim 2 , wherein the smart enhancement step comprises a sub-resolution assist feature (SRAF) process, a smart filling process, or a combination thereof, and the additional smart enhancement step comprises an inverse lithography technology (ILT) process.
4. The method according to claim 1 , wherein the one or more layout criteria comprise one or more optical parameters or their mathematical derivatives, the one or more optical parameters including a maximum intensity, a minimum intensity, a curvature, a contrast, a slope, a normalized image log slope (NILS), a classified threshold on resist profile, or a combination thereof.
5. The method according to claim 1 , wherein the threshold value is an integer greater than one.
6. The method according to claim 1 , wherein the layout polishing step performs a selective biasing step on one or more out-of-criteria layout portions of an output generated by the OPC step.
7. An apparatus comprising:
at least one processor; and
at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus to perform at least the following:
receiving an input data stream of an integrated circuit (IC) design layout;
correcting identified outliers in the IC design layout by way of an iterative repair loop comprising steps of:
performing one or more iterations of an optical proximity correction (OPC) step and a layout polishing step on the input data stream;
performing a smart enhancement step if an output of a last iteration of the OPC step fails to satisfy one or more layout criteria and if a number of the one or more iterations satisfies a threshold value, the smart enhancement step comprising an inverse lithography technology (ILT) process;
cross-linking, by the processor, a base optical rule check (ORC) process with the OPC step; and
performing, by the processor, pattern classification during the one or more iterations of the OPC step,
wherein the pattern classification is based on a pattern matching database or one or more compensation tables.
8. The apparatus according to claim 7 , wherein the apparatus is further configured to:
perform an additional OPC step after the smart enhancement step; and
perform an additional smart enhancement step if an output of the additional OPC step fails to satisfy the one or more layout criteria.
9. The apparatus according to claim 8 , wherein the smart enhancement step comprises a sub-resolution assist feature (SRAF) process, a smart filling process, or a combination thereof, and the additional smart enhancement step comprises an inverse lithography technology (ILT) process.
10. The apparatus according to claim 7 , wherein the one or more layout criteria comprise one or more optical parameters or their mathematical derivatives, the one or more optical parameters including a maximum intensity, a minimum intensity, a curvature, a contrast, a slope, a normalized image log slope (NILS), a classified threshold on resist profile, or a combination thereof.
11. The apparatus according to claim 7 , wherein the threshold value is an integer greater than one.
12. The apparatus according to claim 7 , wherein the layout polishing step performs a selective biasing step on one or more out-of-criteria layout portions of an output generated by the OPC step.
13. A computer-implemented method comprising:
receiving, by way of a processor, an input data stream of an integrated circuit (IC) design layout;
correcting, by the processor, identified outliers in the IC design layout by way of an iterative repair loop comprising steps of:
performing one or more iterations of an optical proximity correction (OPC) step and a layout polishing step on the input data stream;
performing, by the processor, a smart enhancement step if an output of a last iteration of the OPC step fails to satisfy one or more layout criteria and if a number of the one or more iterations satisfies a threshold value, the smart enhancement step comprising an inverse lithography technology (ILT) process;
performing, by the processor, an additional OPC step after the smart enhancement step;
performing, by the processor, an additional smart enhancement step if an output of the additional OPC step fails to satisfy the one or more layout criteria;
cross-linking, by the processor, a base optical rule check (ORC) process with the OPC step; and
performing, by the processor, pattern classification during the one or more iterations of the OPC step,
wherein the pattern classification is based on a pattern matching database or one or more compensation tables, and
wherein the one or more layout criteria comprise one or more optical parameters and the threshold value is an integer greater than one.