IP Library Granted Patent US 9,318,378
Granted Patent B2
US 9,318,378 · App. 10/923,123 · Granted Apr 19, 2016

Slot designs in wide metal lines

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Quick Facts
Patent No.
US 9,318,378
App. No.
10/923,123
Granted
Apr 19, 2016
Kind
B2
Abstract

A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug.

Claims (43)

1. A method of fabricating an interconnection comprising:

providing a substrate prepared with a dielectric layer; and

forming a continuous conductive line in the dielectric layer comprising

patterning the dielectric layer to form a trench in the dielectric layer corresponding to the continuous conductive line, wherein the patterning forms within the trench with at least one dielectric structure positioned in a portion of the trench that is proximal to the continuous conductive line having a via plug in communication therewith, and

filling the trench with a conductive material that surrounds the at least one dielectric structure to form the continuous conductive line having at least one dielectric structure therein, wherein the dielectric structure creates a partial discontinuity within the continuous conductive line.

2. The method of claim 1 wherein the dielectric structure is of a sufficient dimension to reduce stress related defects in the continuous conductive line and the via plug in a via level which is in communication with the continuous conductive line in proximity of the dielectric structure.

3. The method of claim 1 wherein:

the dielectric structure is of a sufficient size to reduce stress related defects in the continuous conductive line and the via plug in a via level in communication with the continuous conductive line in proximity of the dielectric structure; and

the conductive material comprises copper.

4. The method of claim 1 wherein the patterning the dielectric layer to form the trench includes a plurality of dielectric structures in the continuous conductive line, the dielectric structures are of sufficient size to reduce stress related defects in the continuous conductive line and the via plug in communication with the continuous conductive line in proximity of the dielectric structures.

5. The method of claim 4 wherein:

the via plug is located on a bottom surface or a top surface of the continuous conductive line; and

the continuous conductive line containing the dielectric structures comprises a wide conductive line and the via plug is in communication with a narrow conductive line.

6. The method of claim 4 wherein the dielectric structures are completely within the trench such that the dielectric structures form dielectric islands within the continuous conductive line.

7. The method of claim 1 wherein:

the patterning the dielectric layer to form the trench includes a plurality of dielectric structures in the continuous conductive line, the dielectric structures are of sufficient size to reduce stress related defects in the continuous conductive line and the via plug in communication with the continuous conductive line in proximity of the dielectric structures; and

the conductive material comprises copper.

8. The method of claim 7 wherein:

the via plug is located on a bottom surface or a top surface of the continuous conductive line; and

the continuous conductive line containing the dielectric structures comprises a wide conductive line and the via plug is in communication with a narrow conductive line.

9. The method of claim 2 wherein said dielectric structures comprises a geometric shape including rectangular shape, L-shape, curve shape or a combination thereof.

10. A method of fabricating an interconnection comprising:

providing a substrate prepared with a dielectric layer; and

forming a continuous conductive line in the dielectric layer comprising

patterning the dielectric layer to form a trench in the dielectric layer corresponding to the continuous conductive line, wherein the patterning forms within the trench with at least one dielectric structure positioned in a portion of the trench, and

filling the trench with a conductive material that surrounds the at least one dielectric structure to form the continuous conductive line having the at least one dielectric structure therein, wherein the dielectric structure creates a partial discontinuity within the continuous conductive line, the dielectric structure is disposed within a distance from a via plug in a via level which is in communication with the continuous conductive line.

11. The method of claim 10 wherein a minimum distance away from the via plug is between about 0.05 μm and 0.12 μm and a maximum distance between the dielectric structure and the via plug is between about 0.855 and 1.205 μm.

12. The method of claim 10 wherein the dielectric structure is of a sufficient size to reduce stress related defects in the continuous conductive line and the via plug.

13. The method of claim 12 wherein the dielectric structure comprises:

a width between about 135 and 315% of an effective diameter of the via plug; and

a total length between about 265 and 1380% of the effective diameter of the via plug.

14. The method of claim 10 wherein patterning the dielectric layer to form the trench includes a plurality of dielectric structures in the continuous conductive line discontinuously surround the via plug.

15. The method of claim 14 wherein the dielectric structures form a plurality of geometrically discontinuous concentric rows of structures in the continuous conductive line around the via plug.

16. The method of claim 15 wherein:

a minimum distance between the dielectric structures and the via plug is about 26 and 63% of an effective diameter/width of the via plug; and

a maximum distance between the dielectric structures and the via plug is between 0.855 and 2.055 μm.

17. A method of fabricating an integrated circuit comprising:

providing a substrate prepared with a dielectric layer;

patterning the dielectric layer to form a trench in the dielectric layer corresponding to a continuous conductive line, wherein the trench includes a dielectric structure within the trench; and

filling the trench with conductive material that surrounds the dielectric structure to form the continuous conductive line, wherein the continuous conductive line contains the dielectric structure therein, the dielectric structure creates a partial discontinuity within the continuous conductive line, wherein the dielectric structure is positioned in a portion of the trench that is proximal to the conductive line which has a via plug in communication therewith.

18. A method of fabricating a device comprising:

providing a substrate prepared with a dielectric layer corresponding to an interconnect level of the device; and

forming a continuous conductive line in the interconnect level of the dielectric layer, wherein the continuous conductive line surrounds a dielectric structure within the continuous conductive line, the dielectric structure partially interrupt the continuous conductive line, wherein the dielectric structure is positioned in a portion of the conductive line which has a via plug in communication therewith.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 19, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Reel/Frame 054481/0673 →
SECURITY AGREEMENT Recorded Nov 27, 2018
From: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 047660/0203 →
CHANGE OF NAME Recorded Mar 15, 2016
From: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
To: CHARTERED SEMICONDUCTOR MANUFACTURING PTE. LTD.
Reel/Frame 038211/0402 →
CHANGE OF NAME Recorded Mar 15, 2016
From: CHARTERED SEMICONDUCTOR MANUFACTURING PTE. LTD.
To: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Reel/Frame 038211/0412 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2005
From: LIM, YEOW KHENG; LEE, TAE JONG; HSIA, LIANG CHOO; PEY, KIN LEONG; SEE, ALEX; VIGAR, DAVID
To: CHARTERED SEMICONDUCTOR MANUFACTURING LTD
Reel/Frame 016080/0336 →