Defect isolation methods and systems
View Patent ↗A test system and method for testing integrated circuits with improved defect localization is disclosed. A laser is used to perturb a device under test (DUT) at a test location. A tester tests the DUT with a test pattern and compares test results with compare vectors in a prior failure log. When a failure signature is matched, a failure signal is generated, indicating that the test location is a failed location. Comparing the test results with the compare vectors in the prior failure log and generating the failure signal when the failure signature is detected reduces artifacts from testing, shortening debug turnaround time.
1. A test system for testing devices comprising:
a scanning microscope module, the scanning microscope module, when testing a device under test (DUT), is configured to perturb the DUT with a laser at a test (pixel) location; and
a test module, the test module comprises
a test unit,
a reference failure log containing prior failing compare vectors of interest,
a comparator unit, wherein the comparator unit comprises
a first in first out storage for storing the failing compare vectors of the reference failure log, and
a comparator logic for comparing the failing compare vectors with test vectors from the test unit, the comparator logic generates a failure signal if a test result of a test run matches a prior failure signature, and
wherein the test module is configured to
perform the test run at a test location of the DUT with a test pattern,
compare test vectors of the test run with the prior failing compare vectors of interest in the reference failure log by the comparator unit, and
generate a comparator trigger pulse if failing test vectors match the prior failure signature, the trigger pulse indicates that the test location of the DUT is a failed location.
2. The test system of claim 1 wherein the scanning microscope module comprises:
a stage for mounting the DUT when testing the DUT;
a laser source unit for generating a beam;
a scanner unit for scanning the beam across the DUT;
a focusing unit for focusing the beam onto a backside of the DUT;
a photodetector unit for detecting a reflected beam from the DUT and generating a photodetector output signal; and
an image processing unit for processing the photodetector output signal to generate a reflected image of the DUT.
3. The system of claim 2 wherein the failure signal is overlaid onto the reflected image of the DUT at the test location of the DUT corresponding to the comparator trigger pulse.
4. The system of claim 1 wherein the reference failure log contains the failing compare vectors of interest obtained from a sort test.
5. The system of claim 1 wherein the prior failure signature comprises a defined subset of the failing compare vectors in the reference failure log.
6. The system of claim 5 wherein the number of the failing compare vectors contained in the defined subset depends on a desired test stringency.
7. The system of claim 1 wherein generating the trigger pulse only when the test result matches the prior failure signature reduces the number of unwanted artifact failure signals from testing.
8. The system of claim 1 wherein the comparator unit is integrated into the test unit.
9. The system of claim 8 wherein generating the trigger pulse only when the test result matches the prior failure signature reduces the number of unwanted artifact failure signals from testing.
10. A method of testing a device under test (DUT) comprising:
providing a test pattern comprising test vectors with corresponding cycle numbers;
providing a prior failure log comprising prior failing compare vectors of interest from the test pattern, the failing compare vectors include the corresponding cycle numbers to the test pattern; and
testing the DUT,
wherein testing comprises testing at a test location by
perturbing the DUT at the test location with a laser,
performing a test run of the test pattern at the test location,
comparing test vectors with the failing compare vectors of the prior failure log using a comparator unit, wherein the comparator unit comprises
a first in first out storage logic for storing the failing compare vectors of the prior failure log, and
a comparator logic for comparing the failing compare vectors with the test vectors from the test unit, the comparator logic generates failure signal if test result of a test run matches a prior failure signature, and
generating a comparator trigger pulse if failing test vectors matches the prior failure signature, wherein the trigger pulse indicates that the test location of the DUT is a failed location.
11. The method of claim 10 wherein the prior failure log is obtained from a sort test.
12. The method of claim 10 wherein:
the test location corresponds to a pixel location of a reflected image of the DUT; and
the comparator trigger pulse causes a failing signal to be overlaid onto the reflected image at the corresponding pixel location.
13. The method of claim 10 wherein comparing the test vectors comprises comparing corresponding test vectors of the failing compare vectors of the prior failure log.
14. The method of claim 10 wherein testing the DUT performs a test cycle on the DUT, the test cycle comprises:
a) perturbing the DUT at a first test location with a laser,
b) performing the test run of the test pattern at the first test location,
c) comparing the test vectors with the failing compare vectors of the prior failure log, and
d) generating the comparator trigger pulse if the failing test vectors matches a prior failure signature, wherein the trigger pulse indicates that the test location of the DUT is a failed location; and
repeating steps a, b, c and d for the next test location until all test locations of the DUT are tested.
15. The method of claim 14 wherein comparing the test vectors comprises comparing corresponding test vectors of the failing compare vectors of the prior failure log.
16. The method of claim 10 wherein the failure signature comprises a defined subset of failing compare vectors in the reference failure log.
17. The method of claim 16 wherein the number of failing compare vectors contained in the defined subset depends on a desired test stringency.
18. The method of claim 14 wherein comparing the test vectors with the failing compare vectors of the prior failure log and generating the comparator trigger pulse, if the failing test vectors matches the prior failure signature, reduces the number of unwanted artifact failure signals from testing.
19. A test system for testing devices to localize defects comprising:
a scanning microscope module, the scanning microscope module, when testing a device under test (DUT), is configured to perturb the DUT with a laser at a test (pixel) location; and
a test module, the test module comprises
a test unit,
a reference failure log containing prior failing compare vectors of interest,
a comparator unit, wherein the comparator unit comprises
a first in first out storage logic for storing the failing compare vectors of the reference failure log, and
a comparator logic for comparing the failing compare vectors with the test vectors from the test unit, the comparator logic generates the failure signal if the test result matches a prior failure signature, and wherein the test module is configured to
perform a test run at the test location of the DUT with a test pattern,
compare test vectors of the test run with the prior failing compare vectors of interest in the reference failure log by the comparator unit, and
generate a comparator trigger pulse only if failing test vectors match the prior failure signature, the trigger pulse indicates that the test location of the DUT is a failed location.
20. The system of claim 19 wherein the comparator unit is integrated into the test unit.