Multi-time programmable device
View Patent ↗Devices and methods for forming a device are presented. The device includes a substrate having a device region and first and second isolation regions surrounding the device region. The device includes a multi-time programmable (MTP) memory cell having a single transistor disposed on the device region. The transistor includes a gate having a gate electrode over a gate dielectric which includes a programmable resistive layer. The gate dielectric is disposed over a channel region having first and second sub-regions in the substrate. The gate dielectric disposed above the first and second sub-regions has different characteristics such that when the memory cell is programmed, a portion of the programmable resistive layer above one of the first or second sub-region is more susceptible for programming relative to portion of the programmable resistive above the other first or second sub-region.
1. A memory device comprising:
a substrate including a device region that comprises a channel region, the channel region including a first channel sub-region and a second channel sub-region; and
a multi-time programmable (MTP) memory cell having a single transistor, wherein the single transistor includes:
a gate structure including a transitional metal oxide layer disposed over the first channel sub-region and the second channel sub-region, a metal gate electrode disposed on the transitional metal oxide layer, and a buffer layer, wherein the metal gate electrode covers an entire top surface of the transitional metal oxide layer, the transitional metal oxide layer includes a first portion that overlaps the first channel sub-region, the transitional metal oxide layer includes a second portion that overlaps the second channel sub-region, the first portion of the transitional metal oxide layer directly contacts a top surface of the substrate, the buffer layer is disposed between the second portion of the transitional metal oxide layer and the second channel sub-region, the buffer layer directly contacts the top surface of the substrate, and the buffer layer includes titanium.
2. The memory device of claim 1 further comprising:
an isolation region in the substrate, the isolation region arranged to partially underlap the second portion of the transitional metal oxide layer.
3. The memory device of claim 2 wherein the MTP memory cell includes a heavily doped region disposed adjacent to the first channel sub-region, and the second channel sub-region is disposed adjacent to the isolation region.
4. The memory device of claim 2 wherein a topmost surface of the second portion of the transitional metal oxide layer is higher than a topmost surface of the first portion of the transitional metal oxide layer relative to the channel region.
5. A method of forming a multi-time programmable (MTP) non-volatile memory cell, the method comprising:
providing a substrate;
forming a gate structure of a single transistor over a channel region in the substrate, the channel region including a first channel sub-region and a second channel sub-region, wherein forming the gate structure comprises forming a metal gate electrode over a transitional metal oxide layer, the metal gate electrode covers an entire top surface of the transitional metal oxide layer, a first portion of the transitional metal oxide layer overlaps the first channel sub-region, and a second portion of the transitional metal oxide layer overlaps the second channel sub-region,
wherein the first portion of the transitional metal oxide layer directly contacts a top surface of the substrate, a buffer layer is disposed between the second portion of the transitional metal oxide layer and the second channel sub-region, the buffer layer directly contacts the top surface of the substrate, and the buffer layer includes titanium.
6. The method of claim 5 further comprising:
forming an isolation region in the substrate,
wherein the isolation region is arranged to partially underlap the second portion of the transitional metal oxide layer.
7. The method of claim 6 wherein a topmost surface of the second portion of the transitional metal oxide layer is higher than a topmost surface of the first portion of the transitional metal oxide layer relative to the channel region.
8. The method of claim 6 wherein the MTP memory cell includes a heavily doped region disposed adjacent to the first channel sub-region, and the second channel sub-region is disposed adjacent to the isolation region.