Back-gated non-volatile memory cell
A memory device and a method of making the same are presented. The memory device includes a substrate and a memory cell formed on the substrate. The memory cell includes a single transistor. The single transistor includes a first gate on the substrate which functions as a control gate and a second gate embedded in the substrate which functions as a select gate.
1. A non-volatile memory device comprising:
a substrate having a non-volatile memory cell region, the substrate includes a buried oxide (BOX) layer between a surface substrate layer and a base substrate layer;
at least one isolation region in the substrate, wherein the at least one isolation region isolates the non-volatile memory cell region from other active regions, the isolation region extends from a top surface of the surface substrate layer to a depth deeper than the BOX layer;
a first polarity type band/well disposed within the base substrate layer, wherein the first polarity type band/well includes a depth shallower than a bottom of the at least one isolation region; and
a non-volatile memory (NVM) cell disposed on the substrate in the memory cell region, wherein the non-volatile memory cell comprises a transistor, the transistor includes
a first gate of the memory cell disposed on a surface of the surface substrate layer, the first gate includes a charge storage layer, the first gate functions as a control gate of the memory cell, and
a second gate of the memory cell disposed in the base substrate layer, wherein the second gate is configured as a select gate of the NVM cell.
2. The memory device of claim 1 wherein the first gate is coupled to a control gate terminal and the second gate is coupled to a back gate terminal, wherein the NVM cell is selected or accessed by applying a corresponding bias to the control gate terminal and the back gate terminal to perform program, erase or read operations.
3. The memory device of claim 1 wherein the charge storage layer comprises a floating gate.
4. The memory device of claim 1 wherein:
the surface substrate layer comprises silicon; and
the second gate is a back gate to the first gate and the second gate is embedded in the substrate and is disposed within the base substrate layer, wherein the second gate includes a depth shallower than the first polarity type band/well.
5. The memory device of claim 4 wherein:
the first polarity band/well isolates a second polarity doped back gate control layer from the base substrate layer, wherein the BOX layer and back gate control layer serve as the second gate to control the memory device threshold voltage.
6. The memory device of claim 1 wherein the thickness of the surface substrate layer is less than about 30 nm and the thickness of the BOX layer is less than about 5 nm.
7. The memory device of claim 1 wherein the first gate comprises a control gate electrode disposed over the charge storage layer.
8. The memory device of claim 7 wherein the charge storage layer is isolated from the control gate electrode and surface substrate layer by dielectric layers.
9. A method for forming a non-volatile memory device comprising:
providing a substrate, the substrate includes a buried oxide (BOX) layer between a surface substrate layer and a base substrate layer;
forming at least one shallow trench isolation (STI) region in the substrate, wherein the STI region extends from a top surface of the surface substrate layer and partially into a portion of the base substrate layer;
performing a first implant to form a first polarity well within the base substrate layer, wherein the first polarity well comprises a depth shallower than a bottom of the STI region;
performing a second implant to form a second polarity type back gate control layer within the base substrate layer, wherein the back gate control layer comprises a depth shallower than a bottom of the first polarity well; and
forming a non-volatile memory module on the substrate, wherein forming the non-volatile memory module comprises
forming a first gate on a surface of the surface substrate layer, the first gate includes a charge storage layer and functions as a control gate of the memory module, and
forming a second gate in the base substrate layer that functions as a select gate of the memory module.
10. The method of claim 9 wherein the surface substrate layer and the base substrate layer comprise silicon.
11. The method of claim 9 wherein the charge storage layer comprises a nitride layer.
12. The method of claim 9 wherein the charge storage layer comprises a floating gate.
13. The method of claim 9 further comprising:
forming a back gate contact opening, wherein the back gate contact opening extends from the top surface of the surface substrate layer to a bottom of the BOX layer;
forming sidewall spacers on sidewalls of the back gate contact opening, wherein the sidewall spacers extend from the top surface of the surface substrate layer to the bottom of the BOX layer; and
filling the back gate contact opening with polysilicon to form a back gate contact.
14. The method of claim 9 wherein the thickness of the surface substrate layer is less than about 30 nm and the thickness of the BOX layer is less than about 5 nm.
15. The method of claim 9 wherein the BOX layer and back gate control layer serve as the second gate to control the memory device threshold voltage.
16. The method of claim 9 wherein the first gate comprises a control gate electrode disposed over the charge storage layer.
17. The method of claim 9 further comprising applying a bias to the back gate control layer to store data in the charge storage layer of the first gate of the non-volatile memory module.
18. A method for forming a device comprising:
providing a substrate, the substrate includes an insulator layer between a body substrate layer and a base substrate layer;
forming at least one isolation region in the substrate, wherein the isolation region extends from a top surface of the body substrate layer and partially into a portion of the base substrate layer;
forming a first polarity well within the base substrate layer, wherein the first polarity well comprises a depth shallower than a bottom of the at least one isolation region; and
forming a non-volatile memory module on the substrate, wherein forming the non-volatile memory module comprises
forming a select gate embedded in the substrate, wherein the select gate includes a depth shallower than the first polarity well, and
forming a control gate on a surface of the substrate, the control gate includes a charge storage layer and a gate electrode layer over the charge storage layer.
19. The memory device of claim 1 wherein:
the substrate comprises an array region having a plurality of the NVM cells arranged in rows and columns, wherein each row of NVM cells is commonly coupled to a corresponding first terminal and each column of NVM cells is commonly coupled to a corresponding second terminal; and
wherein biasing a first terminal selects for the corresponding row of NVM cells and biasing a second terminal selects for the corresponding NVM cell along the selected row for access to perform program, erase or read operations.