INTEGRATED CIRCUITS INCLUDING MAGNETIC RANDOM ACCESS MEMORY STRUCTURES AND METHODS FOR FABRICATING THE SAME

1 . An integrated circuit, comprising:

a plurality of magnetic random access memory (MRAM) structures, wherein each of said MRAM structures comprises;

a bottom electrode,

a magnetic tunnel junction stack (MTJ stack) overlying and in electrical communication with said bottom electrode layer, and

a top electrode layer overlying and in electrical communication with said MTJ stack; and

a spin-on dielectric layer at least partially encapsulating said MRAM structures with said spin-on dielectric layer disposed between adjacent MRAM structures;

wherein said MRAM structure further comprises a contact disposed on said top electrode layer; and

wherein said MRAM structure further comprises a first hardmask layer overlying said top electrode layer with said contact extending through said first hardmask layer.

2 . (canceled)

3 . (canceled)

4 . The integrated circuit of claim 3 , wherein said MRAM structure further comprises a second hardmask layer overlying said first hardmask layer with said contact extending through said second hardmask layer.

5 . The integrated circuit of claim 3 , further comprising:

a first interlayer dielectric layer (ILD layer);

a metallization layer disposed within said first ILD layer; and

a conductive via structure disposed on and in electrical communication with said metallization layer;

wherein said bottom electrode overlies and is in electrical communication with said conductive via structure.

6 . The integrated circuit of claim 5 , further comprising:

a passivation layer overlying said metallization layer; and

a second ILD layer overlying said passivation layer with said bottom electrode overlying said second ILD layer;

wherein said conductive via structure extends through said passivation layer and said second ILD layer to said bottom electrode.

7 . The integrated circuit of claim 1 , further comprising a logic portion with said spin-on dielectric layer at least partially encapsulating said logic portion.

8 . The integrated circuit of claim 7 , wherein said spin-on dielectric layer has a spin-on dielectric bottom surface adjacent said bottom electrode layer and a spin-on dielectric top surface opposite said spin-on dielectric bottom surface with a first spin-on dielectric height defined therebetween proximate said MRAM structure and a second spin-on dielectric height defined therebetween proximate said logic portion, and said first spin-on dielectric height is substantially the same as said second spin-on dielectric height.

9 . The integrated circuit of claim 1 , wherein said MTJ stack comprises:

a fixed layer overlying said bottom electrode;

a first tunnel barrier layer overlying said fixed layer;

a free layer overlying said first tunnel barrier layer; and

a second tunnel barrier layer overlying said free layer.

10 . The integrated circuit of claim 9 , wherein said MRAM structure further comprises a first veil and a second veil adjacent to said fixed layer, said first tunnel barrier layer, and said first hardmask layer with said MTJ stack disposed therebetween.

11 . A method for fabricating an integrated circuit comprising a plurality of magnetic random access memory (MRAM) structures, said method comprising:

forming the MRAM structures comprising;

forming a bottom electrode layer;

forming a magnetic tunnel junction stack (MTJ stack) overlying and in electrical communication with the bottom electrode layer,

forming a top electrode layer overlying and in electrical communication with the MTJ stack, and

forming a first hardmask layer overlying the top electrode layer with the first hardmask layer; and

depositing a spin-on dielectric material to form a spin-on dielectric layer at least partially encapsulating the MRAM structures with the spin-on dielectric layer disposed between adjacent MRAM structures.

12 . The method of claim 11 , wherein the first hardmask layer has a first hardmask top surface.

13 . The method of claim 12 , further comprising etching the spin-on dielectric layer to expose the first hardmask top surface of the first hardmask layer.

14 . The method of claim 12 , further comprising forming a second hardmask layer overlying the top surface of the first hardmask layer.

15 . The method of claim 14 , wherein forming the MRAM structures further comprises forming a contact on the top electrode layer, the contact extending through the first hardmask layer and the second hardmask layer.

16 . The method of claim 12 , wherein forming the MTJ stack comprises:

forming a fixed layer overlying the bottom electrode layer;

forming a first tunnel barrier layer overlying the fixed layer;

forming a free layer overlying the first tunnel barrier layer; and

forming a second tunnel barrier layer overlying the free layer.

17 . The method of claim 16 , wherein forming the MRAM structures further comprises etching the fixed layer, the first tunnel layer, and the first hardmask layer to form a first veil and a second veil adjacent the fixed layer, the first tunnel layer, and the first hardmask layer with the MTJ stack therebetween.

18 . The method of claim 11 , wherein the integrated circuit further comprises a logic portion, and depositing the spin-on dielectric material further comprises depositing the spin-on dielectric material to form the spin-on dielectric layer at least partially encapsulating the logic portion.

19 . The method of claim 11 , wherein forming the MRAM structures further comprises:

depositing a bottom electrode material to form a bottom electrode layer; and

etching a portion of the bottom electrode layer between adjacent MRAM structures to form a bottom electrode.

20 . The method of claim 11 , further comprising:

forming a first interlayer dielectric layer (ILD layer);

forming a metallization layer disposed within the first ILD layer; and

forming a conductive via structure disposed on and in electrical communication with the metallization layer;

wherein the bottom electrode layer overlies and is in electrical communication with the conductive via structure.

21 . The integrated circuit of claim 1 , wherein said spin-on dielectric layer is formed from a spin-on dielectric material comprising a spin-on-glass (SOG) material.