Non-volatile memory utilizing impact ionization and tunnelling and method of manufacturing thereof

1. A method of manufacturing a non-volatile memory device, the method comprising:

providing a substrate;

forming a source region within the substrate, the source region comprising dopants of a first conductivity type;

forming a drain region within the substrate, the drain region comprising dopants of a second conductivity type;

forming a gate structure having at least a portion embedded in the substrate between the source region and the drain region, and wherein the gate structure comprises a tunnel oxide layer, a floating gate formed over the tunnel oxide layer and a control gate formed over the floating gate;

forming an ionization impact region between the source region and the gate structure; and

forming a halo region in the drain region at a location adjacent the gate structure, the halo region comprising dopants of the first conductivity type.

2. The method as set forth in claim 1 further comprising:

forming a select gate structure at a location adjacent to the gate structure and having at least a portion positioned between the gate structure and the drain region.

3. The method as set forth in claim 1 further comprising:

forming a select gate structure adjacent the floating gate, the select gate structure having a top surface substantially planar to both a top surface of the control gate and a top surface of the floating gate, a first sidewall adjacent a vertical wall of the floating gate, and a second sidewall and a bottom surface adjacent the tunnel oxide layer.

4. The method as set forth in claim 1 further comprising:

forming a halo region within the drain region and doping the halo region with dopants of the first conductivity type.

5. A non-volatile memory device comprising:

a silicon substrate having a narrow bandgap layer of material disposed thereabove;

a source region having dopants of a first type disposed within a portion of the narrow bandgap layer and within a portion of the silicon substrate;

a drain region having dopants of a second type disposed within a portion of the narrow bandgap layer and within a portion of the silicon substrate;

a halo region formed as a portion of the drain region, the halo region having dopants of the first type;

at least a portion of a gate structure embedded within the bandgap layer of material between the source region and the drain region, the gate structure comprising a tunnel oxide layer, a floating gate formed over the tunnel oxide layer and a control gate formed over the floating gate;

an impact ionization region disposed between the source region and the gate structure; and

wherein the memory device is configured to perform a write operation using an ionization impact process and perform a read operation using a tunneling process.

6. The non-volatile memory device as set forth in claim 5 further comprising:

a select gate comprising,

a top surface substantially planar to both a top surface of the control gate and a top surface of the floating gate,

a first sidewall adjacent a vertical wall of the floating gate, and

a second sidewall and a bottom surface adjacent the tunnel oxide layer.

7. A non-volatile memory device configured to perform a write operation using an ionization impact process and perform a read operation using a tunneling process, the memory device further comprising:

a substrate;

a source region within the substrate and having a first conductivity;

a drain region within the substrate and having a second conductivity;

a metal connector contacting the drain region;

a gate structure comprising,

a tunnel oxide layer,

a floating gate formed over the tunnel oxide layer, and

a control gate formed over the floating gate; and

a halo region formed within the drain region wherein the halo region is located adjacent to the gate structure and comprises dopants of the first conductivity type.

8. The non-volatile memory device as set forth in claim 7 , wherein a portion of the tunnel oxide layer is formed as a vertical wall substantially adjacent to the halo region, and the halo region is disposed within the drain region and has a depth less than a depth of the drain region.