Method of forming split-gate cell for non-volative memory devices
View Patent ↗Fabrication of a slim split gate cell and the resulting device are disclosed. Embodiments include forming a first gate on a substrate, the first gate having an upper surface and a hard-mask covering the upper surface, forming an interpoly isolation layer on side surfaces of the first gate and the hard-mask, forming a second gate on one side of the first gate, with an uppermost point of the second gate below the upper surface of the first gate, removing the hard-mask, forming spacers on exposed vertical surfaces, and forming a salicide on exposed surfaces of the first and second gates.
1. A device comprising: a first gate on a substrate, the first gate having an upper surface; an interpoly isolation layer or charge storage layer on side surfaces of the first gate and
extending above the upper surface of the first gate;
a second gate adjacent to the interpoly isolation layer or charge storage layer on a first side of the first gate, the second gate having a spacer shape and having an uppermost point of the second gate below the upper surface of the first gate;
spacers formed on exposed vertical surfaces of the first and second gates and the interpoly isolation layer;
a salicide formed on exposed non-vertical surfaces of the first and second gates and the substrate; and
wherein the first gate is one of a select gate and a control gate, and the second gate is the other of a select gate and a control gate, wherein an uppermost point of the interpoly isolation layer or charge storage layer on the first side is higher than an uppermost point of the second side opposite to the first side and an uppermost point of the first gate is lower than the uppermost point of the interpoly isolation layer or charge storage layer on the second side.
2. The device according to claim 1 , wherein the interpoly isolation layer comprises an oxide.
3. The device according to claim 1 , wherein the interpoly isolation layer comprises a nitride memory storage layer or a nanocrystal layer.
4. The device according to claim 3 , further comprising the interpoly isolation layer between the second gate and the substrate.
5. The device according to claim 3 , further comprising the interpoly dielectric layer between the first and second gates.