Split-gate flash memory exhibiting reduced interference
View Patent ↗A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack.
1. A method comprising:
providing a memory gate stack over a substrate; providing a word gate over the substrate;
and providing a dielectric spacer between the word gate and the memory gate stack, the dielectric spacer comprising a low-k layer and a first high-k layer each layer being formed on the substrate to a same height over the entire length of the low-k and first high-k layers, the dielectric spacer occupying the entire space between the memory gate stack and the word gate.
2. The method according to claim 1 , comprising providing the dielectric spacer such that the first high-k layer is proximate a first side surface of the memory gate stack.
3. The method according to claim 2 , comprising providing a work function tuning layer between the memory gate stack and the first high-k layer.
4. The method according to claim 1 , wherein the dielectric spacer comprises a second high-k layer proximate the word gate.
5. The method according to claim 4 , comprising providing a work function tuning layer between the memory gate stack and the first high-k layer and/or between the word gate and the second high-k layer.
6. The method according to claim 1 , comprising removing the dielectric spacer to form a first air gap between the word gate and the memory gate stack.
7. The method according to claim 1 , comprising providing a second dielectric spacer comprising a low-k layer and a high-k layer proximate a second side surface of the memory gate stack.
8. The method according to claim 7 , comprising removing the second dielectric spacer to form a second air gap.
9. The method according to claim 1 , comprising:
providing the memory gate stack over the substrate; providing the dielectric spacer on opposite side surfaces of the memory gate stack, the
dielectric spacer comprising the first high-k layer proximate the opposite side surfaces of the memory gate stack and the low-k layer; and providing the word gate.
10. The method according to claim 9 , comprising: depositing a high-k material;
depositing a low-k material; and etching to form the dielectric spacer.
11. The method according to claim 9 , comprising: depositing a high-k material;
etching to form the first high-k layer; depositing a low-k material; and etching to form the low-k layer.
12. The method according to claim 9 , wherein the dielectric spacer comprises a second high-k layer proximate the word gate.