Self-aligned contact for replacement metal gate and silicide last processes
View Patent ↗A high-K/metal gate semiconductor device is provided with larger self-aligned contacts having reduced resistance. Embodiments include forming a first high-k metal gate stack on a substrate between source/drain regions, a second high-k metal gate stack on an STI region, and a first ILD between the metal gate stacks, forming an etch stop layer and a second ILD sequentially over the substrate, with openings in the second ILD over the metal gate stacks, forming spacers on the edges of the openings, forming a third ILD over the second ILD and the spacers, removing the first ILD over the source/drain regions, removing the etch stop layer, the second ILD, and the third ILD over the source/drain regions, adjacent the spacers, and over a portion of the spacers, forming first trenches, removing the third ILD over the second high-k metal gate stack and over a portion of the spacers, forming second trenches, and forming contacts in the first and second trenches.
1. A method comprising:
forming a first high-k metal gate stack on a substrate between source/drain regions, a second high-k metal gate stack on a shallow trench isolation (STI) region, and a first inter layer dielectric (ILD) between the first and second metal gate stacks;
forming an etch stop layer on the first and second metal gate stacks;
forming a second ILD on the etch stop layer, with openings over the first and second gate stacks;
forming first and second spacers on the edges of the openings;
forming a third ILD over the second ILD and the first and second spacers;
removing the first ILD over the source/drain regions and the etch stop layer, the second ILD, and the third ILD over the source/drain regions, adjacent the first spacers, and over a portion of the first spacers, forming first trenches;
removing the third ILD over the second high-k metal gate stack and over a portion of the second spacers, forming second trenches; and
forming contacts in the first and second trenches.
2. The method according to claim 1 , forming the first and second high-k metal gate stacks by:
forming a first dummy gate, having first dummy spacers thereon, on the substrate, and forming a second dummy gate, having second dummy spacers thereon, on the STI region in the substrate;
forming the first ILD over the first and second dummy gates;
chemical mechanical polishing (CMP) the first ILD down to the top of the first and second dummy gates;
removing the first and second dummy gates, forming first and second cavities;
depositing a high-k dielectric layer and a metal work function layer in the first and second cavities, and filling the remainder of the first and second cavities with metal.
3. The method according to claim 2 , comprising CMP until the first and second dummy spacers are planar with the top surface of the first and second dummy gates.
4. The method according to claim 3 , comprising forming the etch stop layer of aluminum oxide (Al 2 O 3 ) or hafnium oxide (HfO 2 ).
5. The method according to claim 4 , comprising forming the openings in the second ILD using a reverse gate mask.
6. The method according to claim 5 , comprising forming the first and second spacers by depositing a nitride material in the openings and etching the nitride.
7. The method according to claim 6 , further comprising CMP subsequent to forming the third ILD.
8. The method according to claim 7 , comprising forming a silicide on the source/drain regions prior to forming the first ILD.
9. The method according to claim 7 , further comprising:
forming a silicide on the source/drain regions subsequent to forming the first and second trenches; and
subsequently forming contacts in the trenches.