High voltage PNP using isolation for ESD and method for producing the same
A method of forming a HV lateral PNP BJT with a pulled back isolation structure and a polysilicon gate covering a part of the NW+HVNDDD base region and a part of the collector extension (HVPDDD) and the resulting device are provided. Embodiments include forming a DVNWELL in a portion of a p-sub; forming a HVPDDD in a portion of the DVNWELL; forming a LVPW in a portion of the HVPDDD; forming a first and a second NW laterally separated in a portion of the DVNWELL, the first and second NW being laterally separated from the HVPDDD; forming a N+ base, a P+ emitter, and a P+ collector in an upper portion of the first and second NW and LVPW, respectively; forming a STI structure between the P+ emitter and P+ collector in a portion of the DVNWELL, HVPDDD, and LVPW, respectively; and forming a SAB layer over the STI structure.
1. A method comprising:
forming a dual voltage n-well (DVNWELL) region in a portion of a p-type substrate (p-sub);
forming a p-type high voltage double diffusion drain (HVPDDD) region in a portion of the DVNWELL region;
forming a low-voltage p-well (LVPW) region in a portion of the HVPDDD region;
forming a first and a second n-well (NW) laterally separated in a portion of the DVNWELL, the first and second NW being laterally separated from the HVPDDD region;
forming a N+ base region, a P+ emitter region, and a P+ collector region in an upper portion of the first NW, the second NW, and the LVPW, respectively;
forming a shallow trench isolation (STI) structure between the P+ emitter and P+ collector regions in a portion of the DVNWELL region, HVPDDD region, and LVPW, respectively, and a plurality of STI structures laterally separated in an upper surface of the p-sub; and
forming a silicide block (SAB) layer over the STI structure, opposite sides of the SAB layer aligned with facing edges of the P+ emitter and P+ collector regions.
2. The method according to claim 1 , comprising forming the STI structure adjacent to the P+ emitter and P+ collector regions and in a portion of the second NW.
3. The method according to claim 2 , further comprising:
forming a n-type high voltage double diffusion drain (HVNDDD) region in a portion of the DVNWELL region adjacent to the HVPDDD region prior to the forming of the first and second NW, the STI structure, and the plurality of STI structures;
forming the first and second NW in a portion of the HVNDDD region; and
forming a polysilicon gate over a portion of the STI structure prior to the forming of the SAB layer, a side of the polysilicon gate aligned with an edge of the P+ emitter region.
4. The method according to claim 1 , comprising forming the STI structure a distance away from the P+ emitter region and adjacent to the P+ collector region.
5. The method according to claim 4 , wherein the distance comprises 0.1 micrometer (μm) to 2 μm.
6. The method according to claim 4 , further comprising:
forming a HVNDDD region in a portion of the DVNWELL region adjacent to the HVPDDD region prior to the forming of the first and second NW, the STI structure, and the plurality of STI structures;
forming the first and second NW in a portion of the HVNDDD region; and
forming a polysilicon gate over a portion of the STI structure prior to the forming of the SAB layer, a side of the polysilicon gate aligned with an edge of the P+ emitter region.
7. The method according to claim 4 , further comprising:
forming a polysilicon gate over a portion of the STI structure prior to the forming of the SAB layer, a side of the polysilicon gate aligned with an edge of the P+ emitter region.
8. The method according to claim 4 , further comprising:
forming a HVNDDD region in a portion of the DVNWELL region adjacent to the HVPDDD region prior to the forming of the first and second NW, the STI structure, and the plurality of STI structures; and
forming the first and second NW in a portion of the HVNDDD region.
9. The method according to claim 1 , comprising forming the SAB layer with a lateral width of 1 μm to 8 μm.
10. A device comprising:
a dual voltage n-well (DVNWELL) region in a portion of a p-type substrate (p-sub);
a p-type high voltage double diffusion drain (HVPDDD) region in a portion of the DVNWELL region;
a low-voltage p-well (LVPW) region in a portion of the HVPDDD region;
a first and a second n-well (NW) being laterally separated in a portion of the DVNWELL, the first and second NW laterally separated from the HVPDDD region;
a N+ base region, a P+ region, and a P+ collector region in an upper portion of the first NW, the second NW, and the LVPW, respectively;
a shallow trench isolation (STI) structure between the P+ emitter and P+ collector regions in a portion of the DVNWELL region, HVPDDD region, and LVPW, respectively, and a plurality of STI structures laterally separated in an upper surface of the p-sub; and
a silicide block (SAB) layer over the STI structure, opposite sides of the SAB layer aligned with facing edges of the P+ emitter and P+ collector regions.
11. The device according to claim 10 , wherein the STI structure is adjacent to the P+ emitter and P+ collector regions and in a portion of the second NW.
12. The device according to claim 11 , further comprising:
a n-type high voltage double diffusion drain (HVNDDD) region in a portion of the DVNWELL region adjacent to the HVPDDD region formed prior to a formation of the first and second NW, the STI structure, and the plurality of STI structures;
the first and second NW in a portion of the HVNDDD region; and
a polysilicon gate over a portion of the STI structure prior to a formation of the SAB layer, a side of the polysilicon gate aligned with an edge of the P+ emitter region.
13. The device according to claim 10 , wherein the STI structure is a distance away from the P+ emitter region and adjacent to the P+ collector region.
14. The device according to claim 13 , wherein the distance comprises 0.1 micrometer (μm) to 2 μm.
15. The device according to claim 13 , further comprising:
a HVNDDD region in a portion of the DVNWELL region adjacent to the HVPDDD region, prior to a formation of the first and second NW, the STI structure, and the plurality of STI structures;
the first and second NW in a portion of the HVNDDD region; and
a polysilicon gate over a portion of the STI structure prior to a formation of the SAB layer, a side of the polysilicon gate aligned with an edge of the P+ emitter region.
16. The device according to claim 13 , further comprising:
a polysilicon gate over a portion of the STI structure prior to a formation of the SAB layer, a side of the polysilicon gate aligned with an edge of the P+ emitter region.
17. The device according to claim 13 , further comprising:
a HVNDDD region in a portion of the DVNWELL region adjacent to the HVPDDD region prior to a formation of the first and second NW, the STI structure, and the plurality of STI structures; and
the first and second NW in a portion of the HVNDDD region.
18. The device according to claim 10 , wherein the SAB layer comprises a lateral width of 1 μm to 8 μm.
19. A method comprising:
forming a dual voltage n-well (DVNWELL) region in a portion of a p-type substrate (p-sub);
forming a n-type high voltage double diffusion drain (HVNDDD) region and a p-type high voltage double diffusion drain (HVPDDD) region in a portion of the DVNWELL region, the HVNDDD and HVPDDD regions being adjacent;
forming a first and a second n-well (NW) laterally separated in a portion of the HVNDDD region;
forming a low-voltage p-well (LVPW) region in a portion of the HVPDDD region, the LVPW being laterally separated from the first and second NW;
forming a N+ base region, a P+ emitter region, and a P+ collector region in an upper portion of the first NW, the second NW, and the LVPW, respectively;
forming a shallow trench isolation (STI) structure 0.1 micrometer (μm) to 2 μm away from the P+ collector region and adjacent to the P+ emitter collector region in a portion of the HVNDDD region, HVPDDD region, and LVPW, respectively, and a plurality of STI structures laterally separated in an upper surface of the p-sub; and
forming a silicide block (SAB) layer over the STI structure, opposite sides of the SAB layer aligned with facing edges of the P+ emitter and P+ collector regions.
20. The method according to claim 19 , further comprising:
forming a polysilicon gate over a portion of the second NW, HVNDDD region, HVPDDD region, and STI structure, respectively, prior to the forming of the SAB layer, a side of the polysilicon gate aligned with an edge of the P+ emitter region.