Stress enhanced high voltage device

1. A method of forming a device comprising:

providing a substrate having a device region surrounded by a device isolation region, wherein the device region comprises a source region, a gate region and a drain region defined thereon;

forming a gate in the gate region, a source in the source region and a drain in the drain region to form a transistor;

forming an internal isolation region which comprises isolation material, wherein the internal isolation region displaces the drain from a drain side of the gate and underlaps a portion of the gate on the drain side of the gate;

partially recessing the isolation material of the internal isolation region to form a first secondary trench in the internal isolation region, wherein a width of the first secondary trench is smaller than a width of the internal isolation region;

forming an etch stop (ES) stressor layer over the substrate, wherein the ES stressor layer lines the transistor and first secondary trench without filling the first secondary trench to leave a trench gap; and

forming a dielectric layer on the substrate, the dielectric layer covering the transistor and filling the trench gap over the ES stressor layer.

2. The method of claim 1 wherein the internal isolation region is formed along a channel width direction in the substrate between the gate and drain and the internal isolation region is formed simultaneously with the device isolation region.

3. The method of claim 2 comprises forming a drift well in the substrate between the gate and drain region, underlapping a portion of the gate.

4. The method of claim 3 wherein the drift well encompasses the drain and internal isolation region.

5. The method of claim 1 wherein the device isolation region isolates the device region from other regions of the device.

6. The method of claim 5 comprises forming a device well within the device isolation region.

7. The method of claim 6 wherein the device well encompasses the source, drain, drift well and internal isolation region.

8. The method of claim 1 wherein:

the first secondary trench extends to about 90-100% of the depth of the internal isolation region; and

the ES stressor layer induces a first stress on a channel and a drift well of the device.

9. The method of claim 1 wherein the ES stressor layer comprises dielectric material.

10. The method of claim 9 wherein the ES stressor layer comprises silicon nitride.

11. The method of claim 1 wherein the ES stressor layer induces a first stress on a channel and a drift well of the device.

12. The method of claim 11 wherein the device is an NMOS transistor, and wherein the first stress is a tensile stress.

13. The method of claim 11 wherein the device is a PMOS transistor, and wherein the first stress is a compressive stress.

14. The method of claim 1 wherein:

the source is adjacent to a source side of the gate;

the isolation material of the internal isolation region comprises a dielectric material; and

at least sidewalls of the first secondary trench are surrounded by isolation material of the internal isolation region.

15. The method of claim 1 comprising:

forming a second secondary trench in the device isolation region which is adjacent to and contact the drain region, wherein a width of the second secondary trench is smaller than a width of the device isolation region; and

forming the ES stressor layer also lines the second secondary trench without filling the second secondary trench.

16. A method of forming a semiconductor device comprising:

providing a substrate having a device region surrounded by a device isolation region, the device region comprises an internal isolation region, wherein

the device and internal isolation regions comprise isolation material, and

the device region comprises a source region, a gate region and a drain region defined thereon;

forming a gate in the gate region, a source in the source region and a drain in the drain region, the source and drain are disposed within the substrate and below the gate, wherein the drain is separated from a second side of the gate by the internal isolation region and the source is adjacent to a first side of the gate;

forming a first secondary trench in the isolation material of the internal isolation region and forming a second secondary trench in the isolation material of the device isolation region which is adjacent to and contacts the drain; and

forming an etch stop (ES) stressor layer over the substrate, wherein the ES stressor layer lines the first and second secondary trenches without filling the trenches.

17. The method of claim 16 comprises forming a drift well in the substrate between the gate and drain regions, wherein the drift well underlaps a portion of the gate.

18. The method of claim 16 wherein the ES stressor layer induces a first stress on a channel and a drift well of the device.

19. The method of claim 18 wherein the device is an NMOS transistor, and wherein the first stress is a tensile stress.

20. The method of claim 18 wherein the device is a PMOS transistor, and wherein the first stress is a compressive stress.

21. A method of forming a device comprising:

providing a substrate having a device region, wherein a device isolation region surrounds the device region;

forming a gate in the device region;

forming a first and a second heavily doped region in the device region, wherein the first and second heavily doped regions are disposed within the substrate adjacent to first and second sides of the gate;

forming an internal isolation region which comprises isolation material, wherein the internal isolation region displaces the second heavily doped region from a second side of the gate;

forming at least a first secondary trench in the internal isolation region, wherein a width of the first secondary trench is smaller than a width of the internal isolation region; and

forming an etch stop (ES) stressor layer over the substrate, wherein the ES stressor layer lines the first secondary trench without filling the first secondary trench.

22. The method of claim 21 wherein:

forming at least the first secondary trench also forms a second secondary trench in the device isolation region which is adjacent to and contacts the second heavily doped region; and

forming the ES stressor layer also lines the second secondary trench without filling the second secondary trench.