Method for forming a shallow junction region using defect engineering and laser annealing
View Patent ↗A method for forming a shallow junction region in a crystalline semiconductor substrate and method for fabricating a semiconductor device having the shallow junction region includes a defect engineering step in which first ions are introduced into a first region of the substrate and vacancies are generated in the first region. During the generation of substrate vacancies, the first region remains substantially crystalline. Interstitial species are generated in a second region and second ions are introduced into the second region to capture the interstitial species. Laser annealing is used to activate dopant species in the first region and repair implantation damage in the second region. The defect engineering process creates a vacancy-rich surface region in which source and drain extension regions having high dopant activation and low sheet resistance are created in an MOS device.
1. A method for forming a shallow junction region in a crystalline semiconductor substrate, the method comprising:
introducing first ions into a first region of the substrate and generating substrate vacancies in the first region and generating interstitial species in a second region, wherein the first region remains substantially crystalline; and
introducing second ions into the second region of the substrate and capturing the interstitial species,
whereby a vacancy-rich surface region is created in the substrate.
2. The method of claim 1 , further comprising introducing dopant species into the vacancy-rich surface region and forming an ultra-shallow junction in the first region.
3. The method of claim 2 , wherein introducing first ions comprises introducing one or more of silicon or germanium.
4. The method of claim 2 , wherein introducing first ions comprises introducing ions at a dose of about 10E13 to 10E15 ions per square centimeter and at an energy of about 10 to about 200 KeV.
5. The method of claim 1 , wherein introducing second ions comprises introducing electrically neutral species.
6. The method of claim 5 , wherein introducing second ions comprises introducing one or more of carbon or fluorine.
7. The method of claim 1 further comprising laser annealing the substrate such that the substrate temperature remains below the melting point of the substrate material.
8. The method of claim 1 further comprising:
forming a gate electrode on a surface of the crystalline semiconductor substrate;
forming source and drain extension regions adjacent to the gate electrode; and
laser annealing the crystalline semiconductor substrate.
9. The method of claim 8 , wherein introducing first ions comprises implanting one or more of silicon or germanium.
10. The method of claim 9 , wherein introducing first ions comprises implanting ions at a dose of about 10E13 to 10E15 ions per square centimeter and at an energy of about 10 to about 200 KeV.
11. The method of claim 8 , wherein introducing second ions comprises introducing electrically neutral species.
12. The method of claim 11 , wherein introducing second ions comprises implanting species configured to chemically or electrically bond with the interstitial species.
13. The method of claim 8 , wherein introducing second ions comprises implanting one or more of carbon or fluorine.
14. The method of claim 8 , wherein laser annealing comprises pulsed laser annealing, and wherein the substrate temperature remains below the melting point of crystalline semiconductor material forming the crystalline semiconductor substrate.
15. The of claim 1 further comprising:
forming an MOS device in the crystalline semiconductor substrate, the device including source and drain regions in the substrate separated by a channel region, a gate electrode overlying the channel region and separated therefrom by a gate dielectric layer, and source and drain extension regions in the substrate adjacent to the source and drain regions.
16. The method of claim 15 further comprising laser annealing the substrate to activate the source and drain extension regions, wherein the substrate temperature remains below the melting point of a crystalline semiconductor material forming the crystalline semiconductor substrate.
17. The method of claim 16 further comprising forming silicide regions at a surface region.
18. The method of claim 16 , wherein introducing first ions comprises introducing one or more of silicon or germanium and introducing second ions comprises introducing one or more of carbon or fluorine.
19. The method of claim 16 , wherein introducing second ions comprises introducing electrically neutral species that chemically or electrically bond with the interstitial species.
20. A method, for forming a shallow junction region in a crystalline semiconductor substrate, the method comprising:
introducing first ions into a first region of the substrate and generating substrate vacancies in the first region and generating interstitial species in a second region, wherein the first region remains substantially crystalline; and
introducing second ions into the second region of the substrate and capturing the interstitial species,
whereby a vacancy-rich surface region is created in the substrate
wherein introducing second ions comprises introducing electrically neutral species that chemically or electrically bond with the interstitial species.