Extended drain metal-oxide-semiconductor transistor
Devices and methods for forming a device are disclosed. A substrate is provided. A first body well of a second polarity type is formed in the substrate. A second body well of the second polarity type is formed in the first body well. A bottom of the second body well and a bottom of the first body well are contiguous. Dopant concentrations of the first and second body wells include a graded profile. A transistor of a first polarity type is formed over the substrate. The transistor includes a source and a drain. The source is formed in the second body well.
1. A method for forming a device comprising:
providing a substrate;
forming a second polarity type first body well in the substrate, wherein the first body well is uniformly doped with second polarity type dopants;
forming a second polarity type second body well in the first body well, wherein the second body well is uniformly doped with second polarity type dopants, wherein a bottom of the second body well and a bottom of the first body well are contiguous, and wherein the second body well has a lower dopant concentration than the first body well; and
forming a first polarity type transistor over the substrate, wherein the transistor comprises a gate, a source and a drain, and wherein the source is formed in the second body well and is heavily doped with first polarity type dopants having a larger mass than the dopants of the second body well to produce a box like dopant profile.
2. The method of claim 1 wherein forming the first body well comprising
forming the gate on the substrate; and
implanting second polarity type dopants into the substrate, wherein the gate serves as an implant mask.
3. The method of claim 2 wherein the first body well is doped with the second polarity type dopants having a lighter mass than the dopants in the source.
4. The method of claim 3 wherein the second polarity type dopants comprise boron.
5. The method of claim 1 wherein forming the second body well comprising
forming the gate on the substrate; and
implanting second polarity type dopants into the substrate, wherein the gate serves as an implant mask.
6. The method of claim 5 wherein the second polarity type dopants comprise BF 2 .
7. The method of claim 5 wherein implanting the second polarity type dopants into the substrate comprises a vertical BF 2 implant.
8. The method of claim 1 wherein forming the first polarity type transistor over the substrate comprises:
forming the gate on the substrate; and
implanting first polarity type dopants with large mass into the substrate, wherein the gate serves as an implant mask.
9. The method of claim 8 wherein the first polarity type dopants with large mass comprise arsenic (As).
10. The method of claim 1 wherein the drain and source are asymmetrical doped region.
11. The method of claim 10 wherein the depth of the drain is deeper than the depth of the source.
12. The method of claim 1 wherein substrate is a silicon-on-insulator (SOI) substrate and wherein the SOI substrate comprises a surface silicon layer, a buried oxide (BOX) layer and a bulk silicon layer.
13. The method of claim 12 wherein the drain extends from a top surface of the surface silicon layer to the BOX layer, and the source extends from the top surface of the surface silicon layer to a partial thickness of the surface silicon layer.
14. The method of claim 12 wherein the first and second device well extend from a top surface of the surface silicon layer to the BOX layer.
15. The method of claim 1 further comprising forming a first type drift well in the substrate.
16. The method of claim 1 further comprising forming a body contact of a second polarity type along a channel direction of the transistor.
17. The method of claim 1 wherein the drain is displaced from the gate.
18. A method of forming a device comprising:
providing a substrate;
forming a uniformly doped first body well in the substrate;
forming a uniformly doped second body well in the first body well, wherein a bottom of the second body well and a bottom of the first body well are contiguous, and wherein the second body well has a lower dopant concentration than the first body well; and
forming a first polarity type transistor over the substrate, wherein the transistor comprises a gate, a source and a drain, and wherein the source
is formed in the second body well,
has a depth of a lightly doped drain (LDD) extension, and
is heavily doped with first polarity type dopants having a larger mass than the dopants of the second body well to produce a box like dopant profile, and wherein the first polarity type dopants comprise arsenic (As).
19. The method of claim 18 wherein the first body well is doped with second polarity type dopants, and wherein the second polarity type dopants comprise boron.
20. The method of claim 18 wherein the second body well is doped with second polarity type dopants, and wherein the second polarity type dopants comprise BF 2 .