ESD protection circuit
View Patent ↗A device having a substrate defined with a device region is presented. The device region includes an ESD protection circuit having a transistor. The transistor includes a gate having first and second sides, a first diffusion region disposed adjacent to the first side of the gate and a second diffusion region displaced away from the second side of the gate. The device includes a first device well encompasses the device region and a second device well disposed within the first device well. The second device well encompasses the first diffusion region and at least a part of the gate. The device also includes a third well which is disposed within the second device well and a drain well which encompasses the second diffusion region and extends below the gate.
1. A device comprising:
a substrate defined with a device region, the device region comprises an ESD protection circuit having a transistor, wherein the transistor is devoid of a drift well, the transistor includes
a gate having first and second sides,
a first diffusion region adjacent to the first side of the gate, and
a second diffusion region displaced away from the second side of the gate,
wherein the first and second diffusion regions comprise dopants of a first polarity type;
a first device well encompasses the device region and a second device well disposed within the first device well, wherein the second device well encompasses the first diffusion region and at least a part of the gate without encompassing the second diffusion region;
a third well disposed within the second device well; and
a drain well encompasses the second diffusion region and extends below the gate.
2. The device of claim 1 wherein:
the first device well comprises dopants of the first polarity type; and
the second device well and third well comprise dopants of a second polarity type.
3. The device of claim 2 wherein the first polarity type comprises n type and the second polarity type comprises p type.
4. The device of claim 1 wherein the third well encompasses at least the first diffusion region and a part of the gate.
5. The device of claim 4 wherein the third well comprises a width which is narrower than a width of the second device well.
6. The device of claim 1 wherein the drain well comprises dopants of the first polarity type.
7. The device of claim 6 wherein the first polarity type comprises n type.
8. The device of claim 1 wherein the drain well is wider than the third well.
9. The device of claim 1 wherein a first edge of the third well is below a bottom of a device isolation region adjacent to the first side of the gate and a second edge of the third well is below and in between the first and second sides of the gate.
10. The device of claim 9 wherein:
a first edge of the second device well is below the bottom of the device isolation region adjacent to the first side of the gate and a second edge of the second device well is below and in between the second side of the gate and a first side of the drain well; and
wherein the second edge of the third well and the second edge of the second device well is separated by a distance D o .
11. The device of claim 9 wherein a first edge of the second device well is below the bottom of the device isolation region adjacent to the first side of the gate and a second edge of the second device well is aligned with the second edge of the third well.
12. The device of claim 1 wherein the transistor comprises a silicide block overlapping the gate.
13. A device comprising:
a substrate defined with a device region, the device region comprises an ESD protection circuit having a transistor, wherein the transistor includes
a gate having first and second sides,
a first diffusion region adjacent to the first side of the gate, and
a second diffusion region displaced away from the second side of the gate,
wherein the transistor is devoid of a drift isolation region disposed between the gate and the second diffusion region;
a first device well encompasses the device region and a second device well disposed within the first device well, wherein the second device well encompasses the first diffusion region and at least a part of the gate;
a third well disposed within the second device well; and
a drain well having dopants of a first polarity type encompasses the second diffusion region and extends below the gate.
14. The device of claim 13 wherein:
the first device well comprises dopants of the first polarity type;
the second device well and third well comprise dopants of a second polarity type; and
the first and second diffusion regions comprise dopants of the first polarity type.
15. The device of claim 14 wherein the first polarity type comprises n type and the second polarity type comprises p type.
16. The device of claim 13 wherein the drain well underlaps a portion of the gate.
17. The device of claim 13 wherein a first edge of the third well is below a bottom of a device isolation region adjacent to the first side of the gate and a second edge of the third well is below and in between the first and second sides of the gate.
18. The device of claim 17 wherein:
a first edge of the second device well is below the bottom of the device isolation region adjacent to the first side of the gate and a second edge of the second device well is below and in between the second side of the gate and a first side of the drain well; and
wherein the second edge of the third well and the second edge of the second well is separated by a distance D o .
19. The device of claim 17 wherein a first edge of the second device well is below the bottom of the device isolation region adjacent to the first side of the gate and a second edge of the second device well is aligned with the second edge of the third well.
20. The device of claim 13 wherein the transistor comprises a silicide block overlapping the gate, wherein the silicide block extends partially over the second diffusion region.